View MB90F583CPMC_7147000.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fujitsu microelectronics data sheet copyright?2001-2009 fujitsu microelec tronics limited all rights reserved 2009.5 for the information for microcontrolle r supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90580c series mb90583c/583ca/f583c/f583ca/f584c/f584ca/ mb90587c/587ca/v580b description the mb90580c series is a line of general-purpose, fujitsu microelectronics 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. while inheriting the at architecture of the f 2 mc* 1 family, the instruction set for the f 2 mc-16lx cpu core of the mb90580c series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90580c has an on-chip 32-bit accumulator which enables processing of long-word data. the peripheral resources integrated in the mb90580c series include: an 8/10-bit a/d converter, an 8-bit d/a converter, uarts (sci) 0 to 4, an 8/16-bit ppg timer, 16 -bit i/o timers (16-bit free-run timer, input capture units (icus) 0 to 3, output compare uni ts (ocus) 0 and 1), and an iebus tm controller * 2 . *1: f 2 mc is the abbreviation of fujitsu flexible microcontroller. *2: iebus tm is a trademark of nec corporation. features ? minimum execution time: 62.5 ns/4 mhz oscillation (u ses pll clock multiplication) maximum multiplier = 4 ? maximum memory space 16 mbyte linear/bank access (continued) ds07-13710-7e
mb90580c series 2 ds07-13710-7e ? instruction set optimized for controller applications supported data types: bit, byte, word, and long-word types standard addressing modes: 23 types 32-bit accumulator enhancing high-precision operations signed multiplication/division and extended reti instructions ? enhanced high level language (c) and multitasking support instructions use of a system stack pointer symmetrical instruction set and barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed: 4 byte instruction queue ? enhanced interrupt function up to eight priority levels programmable external interrupt inputs: 8 lines ? automatic data transmission func tion independent of cpu operation up to 16 channels for the extended intelligent i/o service dtp request inputs: 8 lines ? internal rom flash: 128 kbyte (mb90f583c/c a), 256kbyte (mb90f584c/ca) maskrom: 128 kbyte (mb90583c/ca ) , 64 kbyte (mb90587c/ca) ? internal ram flash: 6 kbyte (mb90f583c/ca, mb90f584c/ca) maskrom: 6 kbyte (mb90583c/ca) , 4 kbyte (mb90587c/ca) ? general-purpose ports up to 77 channels (input pull-up resistor settable for: 22 channels. output open drain settable for: 8 channels) ?iebus tm controller * three different data transfer rates selectable mode 0: 3.9 kbps (16 bytes/frame) mode 1: 17.0 kbps (32 bytes/frame) mode 2: 26.0 kbps (128 bytes/frame) *: iebus tm is a trademark of nec corporation. ? a/d converter (rc) : 8 ch 8/10-bit resolution conversion time: 34.7 s (min) , 12 mhz operation ? d/a converter: 2 ch 8-bit resolutions setup time: 12.5 s ?uart : 5 ch ? 8/16 bit ppg : 1 ch 8 bits 2 channels: 16 bits 1 channel: mode switching function provided ? 16 bit reload timer: 3 ch ? 16-bit pwc timer: 1 channel noise filter provided. available to pulse width counter ? 16 bit i/o timer input capture : 4 ch output compare : 2 ch free run timer: 1 ch ? internal clock generator ? time-base counter/watchdog timer: 18-bit (continued)
mb90580c series ds07-13710-7e 3 (continued) ? clock monitor function integrated ? low-power consumption mode sleep mode stop mode hardware standby mode cpu intermittent operation mode ? package: lqfp-100 / qfp-100 ?cmos technology
mb90580c series 4 ds07-13710-7e product lineup (continued) part number item mb90587c/ca mb90583c/ca mb90f583c /ca mb90f584c/ca mb90v580b classification mass-produced products (mask rom) mass-produced products (flash rom) development / evaluation product rom size 64 kbytes 128 kbytes 128 kbytes 256 kbytes none ram size 4 kbytes 6 kbytes 6 kbytes 6 kbytes 6 kbytes clock* 1 two clocks / one clock system two clocks / one clock system two clocks / one clock system two clocks / one clock system two clocks system emulator-specific power supply * 2 ?? ? ? none cpu functions the number of instructions: 340 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock of 16 mhz) interrupt processing time: 1.5 s (at machine clock of 16 mhz, minimum value) ports general-purpose i/o ports (cmos output) general-purpose i/o port (can be set as open-drain) general-purpose i/o ports (input pull-up resistors available) to t a l : : 45 : 8 : 22 : 77 iebus tm controller none communication mode: half-duplex, asynchronous communication multi-master system access control: cdma/cd three modes selectable for different transmission speeds transmit buffer: 8-byte fifo buffer receive buffer: 8-byte fifo buffer timebase timer 18-bit counter interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at os cillation of 4 mhz) watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) watch timer 15-bit counter interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (at oscilla tion of 32.768 khz) 8/16-bit ppg timer number of channels: 1 (8-bit 2 channels) ppg operation of 8-bit or 16-bit a pulse wave of given intervals an d given duty ratios can be output. pulse interval: 62.5 ns to 1 ms (at osc illation of 4 mhz, machine clock of 16 mhz) 16-bit reload timer number of channels: 3 event count provided interval: 125 ns to 131 ms (at oscillation of 4 mhz, machine clock of 16 mhz) pwc timer number of channels: 1 timer function (select the counter timer from three internal clocks.) pulse width measuring function (select the counter timer from three internal clocks.)
mb90580c series ds07-13710-7e 5 (continued) *1: connect the oscillator to both terminals xa0 and xa1 for mb90f587c / 583c / f583c / f584c. *2: it is setting of dip switch s2 when emulation pod (mb2145-507) is used. please refer to the mb2145-507 hardware manual (2 .7 emulator-specific power pin) about details. *3: varies with conditions such as the operating frequency (see section ? electrical characteristics?). assurance for the mb90v580b is given only for operatio n with a tool at a power supply voltage of 4.5 v to 5.5 v, an operating temperature of 0 to +25 c, and an operating freq uency of 1 mhz to 16 mhz. package and corresponding products : available : not available note: : for more information about each package, see section ? package dimensions?. part number item mb90587c/ca mb90583c/ca mb90f583 c/ca mb90f584c/ca mb90v580b 16-bit i/o timer 16-bit free run timer number of channels: 1 overflow interrupts output compare (ocu) number of channels: 2 pin input factor: a match signal of compare register input capture (icu) number of channels: 4 rewriting a register value upon a pi n input (rising, falling, or both edges) dtp/external interrupt circuit number of inputs: 8 started by a rising edge, a falling edge, an ?h? level input, or an ?l? level input. external interrupt circuit or ex tended intelligent i/o service (ei 2 os) can be used. delayed interrupt generation module an interrupt generation module for switching tasks used in real time operating systems. uart0, 1, 2, 3, 4 clock synchronized transmission (62.5 kbps to 1 mbps) clock asynchronized transmission (1202 bps to 9615 bps) transmission can be performed by bi-directional serial transmission or by master/slave connection. a/d converter resolution: 8/10-bit changeable number of inputs: 8 one-shot conversion mode (conv erts selected channel only once) scan conversion mode (converts two or more successive chann els and can program up to 8 channels.) continuous conversion mode (conve rts selected channel repeatedly) stop conversion mode (converts select ed channel and stop operation repeatedly) d/a converter 8-bit resolution number of channels: 2 channels based on the r-2r system low-power consumption (standby) mode sleep/stop/cpu intermittent operation/watch/hardware standby process cmos power supply voltage for operation 4.5 v to 5.5 v* 3 package mb90583c/ca mb90587c/ca mb90f584c/ca mb90f583c/ca fpt-100p-m20 fpt-100p-m06
mb90580c series 6 ds07-13710-7e differences among products memory size in evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. the following items must be taken into consideration. ? the mb90v580b does not have an internal rom, howeve r, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development to ol, enabling selection of rom size by settings of the development tool. ? in the mb90v580b, images from ff4000 h to ffffff h are mapped to bank 00, and fe0000 h to ff3fff h to mapped to bank fe and ff only. (this setting can be changed by configuring the development tool.) ? in the mb90583c/583ca/587c/587ca/f583c /f583ca/f584c/f584ca, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h to bank ff only. iebus tm controller ? mb90587c/ca does not have an iebus tm controller.
mb90580c series ds07-13710-7e 7 pin assignment (top view) (fpt-100p-m20) p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl p34/hrq p33/wrh p35/hak p36/rdy p37/clk p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 v cc p45/sck1 p46/adtg p47 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst pa1 pa0 p97/pot p96/pwc p95/tot2/out1 p94/tot1/out0 p93/tot0/in3 p92/tin2/in2 p91/tin1/in1 p90/tin0/in0 rx * tx * p65/ckot p64/ppg0 p63/ppg1 p62/sck2 p61/sot2 p60/sin2 p87/irq7 p86/irq6 p85/irq5 p84/irq4 p83/irq3 p82/irq2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p21/a17 p20/a16 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss x0a x1a pa2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p71 p72 dvrh dv ss p73/da00 p74/da01 av cc avrh avrl av ss p50/an0/sin3 p51/an1/sot3 p52/an2/sck3 p53/an3 v ss p54/an4/sin4 p55/an5/sot4 p56/an6/sck4 p57/an7 p80/irq0 p81/irq1 md0 md1 md2 hst * : n.c. pin on the mb90587c/ca
mb90580c series 8 ds07-13710-7e (top view) (fpt-100p-m06) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 v cc p45/sck1 p46/adtg p47 c p71 p72 dvrh x0a pa2 rst pa1 pa0 p97/pot p96/pwc p95/tot2/out1 p94/tot1/out0 p93/tot0/in3 p92/tin2/in2 p91/tin1/in1 p90/tin0/in0 rx * tx * p65/ckot p64/ppg0 p63/ppg1 p62/sck2 p61/sot2 p60/sin2 p87/irq7 p86/irq6 p85/irq5 p84/irq4 p83/irq3 p82/irq2 hst md2 x1a p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss dv ss p73/da00 p74/da01 p50/an0/sin3 p51/an1/sot3 p52/an2/sck3 p53/an3 v ss p54/an4/sin4 p55/an5/sot4 p56/an6/sck4 p57/an7 p80/irq0 p81/irq1 md0 md1 av cc avrh avrl av ss * : n.c. pin on the mb90587c/ca
mb90580c series ds07-13710-7e 9 pin description *1: fpt-100p-m06 *2: fpt-100p-m20 (continued) pin no. pin name circuit type function qfp* 1 lqfp* 2 82 80 x0 a oscillator pin 83 81 x1 a oscillator pin 52 50 hst c hardware standby input pin 77 75 rst b reset input pin 85 to 92 83 to 90 p00 to p07 d (cmos/h) general-purpose i/o ports. a pull-up resistor can be assigned (rd07 to rd00=?1?) by the pull- up resistor setting register (rdr0). [these pins are disabled with the output setting (ddr0 register: d07 to d00=?1?).] ad00 to ad07 in external bus mode, the pins function as the lower data i/o or low- er address outputs (ad00 to ad07). 93 to 100 91 to 98 p10 to p17 d (cmos/h) general-purpose i/o ports. a pull-up resistor can be assigned (rd17 to rd10=?1?) by the pull- up resistor setting register (rdr1). [these pins are disabled with the output setting (ddr1 register: d17 to d10 =?1?).] ad08 to ad15 in 16-bit external bus mode, the pins function as the upper data i/o or middle address outputs (ad08 to ad15). 1 to 8 99,100, 1 to 6 p20 to p27 f (cmos/h) general-purpose i/o ports in external bus mode, pins for which the corresponding bit in the hacr register is ?1? function as the a16 to a23 pins. a16 to a23 in external bus mode, pins for which the corresponding bit in the hacr register is ?1? function as the upper address output pins (a16 to a23). 97 p30 f (cmos/h) general-purpose i/o port functions as the ale pin in external bus mode. ale functions as the address latch enable signal pin (ale) in external bus mode. 10 8 p31 f (cmos/h) general-purpose i/o port functions as the rd pin in external bus mode. rd functions as the read strobe output pin (rd ) in external bus mode. 12 10 p32 f (cmos/h) general-purpose i/o port functions as the wrl pin in external bus mode if the wre bit is ?1?. wrl functions as the lower data write strobe output pin (wrl ) in external bus mode. 13 11 p33 f (cmos/h) general-purpose i/o port functions as the wrh pin in 16-bit external bus mode if the wre bit in the epcr register is ?1? wrh functions as the upper data write strobe output pin (wrh ) in external bus mode.
mb90580c series 10 ds07-13710-7e *1: fpt-100p-m06 *2: fpt-100p-m20 (continued) pin no. pin name circuit type function qfp* 1 lqfp* 2 14 12 p34 f (cmos/h) general-purpose i/o port functions as the hrq pin in extern al bus mode if the hde bit in the epcr register is ?1?. hrq functions as the hold request input pin (hrq) in external bus mode. 15 13 p35 f (cmos/h) general-purpose i/o port functions as the hak pin in external bus mode if the hde bit in the epcr register is ?1?. hak functions as the hold acknowledge output pin (hak ) in external bus mode. 16 14 p36 f (cmos/h) general-purpose i/o port functions as the rdy pin in extern al bus mode if the rye bit in the epcr register is ?1?. rdy functions as the external ready in put pin (rdy) in external bus mode. 17 15 p37 f (cmos/h) general-purpose i/o port functions as the clk pin in external bus mode if the cke bit in the epcr register is ?1?. clk functions as the machine cycle clock output pin (clk) in external bus mode. 18 16 p40 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain ou tput port with od40 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d40=?0?).] sin0 uart0 serial data input (sin0) pin. when uart0 is operating for input, this input is used as required and thus the output from any other functi on to the pin must be off unless used intentionally. 19 17 p41 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain ou tput port with od41 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d41=?0?).] sot0 uart0 serial data output pin (sot0). this pin is enabled with the uart0 serial data output enabled. 20 18 p42 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain ou tput port with od42 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d42=?0?).] sck0 uart0 serial clock i/o pin (sck0). this pin is enabled with the uart0 clock output enabled.
mb90580c series ds07-13710-7e 11 *1: fpt-100p-m06 *2: fpt-100p-m20 (continued) pin no. pin name circuit type function qfp* 1 lqfp* 2 21 19 p43 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain output port with od43 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d43=?0?).] sin1 uart1 serial data input (sin1) pin. when uart1 is operating for input, this input is used as required and thus the output from any other functi on to the pin must be off unless used intentionally. 22 20 p44 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain output port with od44 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d44=?0?).] sot1 uart1 serial data output pin (sot1). this pin is enabled with the uart1 serial data output enabled. 24 22 p45 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain output port with od45 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d45=?0?).] sck1 uart1 serial clock i/o pin (sck1). this pin is enabled with the uart1 clock output enabled. 25 23 p46 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain output port with od46 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d46=?0?).] adtg external trigger input pin (adtg) for the a/d converter. 26 24 p47 e (cmos/h) general-purpose i/o port. this pin serves as an open-drain output port with od47 in the open- drain control setting register (odr4) set to ?1?. [the pin is disabled with the input setting (ddr4 register: d47=?0?).] 38 36 p50 g (cmos/h) general-purpose i/o port. an0 analog input pin (an0) for us e during a/d converter operation. sin3 uart3 serial data input pin (sin3). when uart3 is operating for input, this input is used as required and thus the output from any other functi on to the pin must be off unless used intentionally. 39 37 p51 g (cmos/h) general-purpose i/o port. an1 analog input pin (an1) for us e during a/d converter operation. sot3 uart3 serial data output pin (sot3). this pin is enabled with the uart3 serial data output enabled.
mb90580c series 12 ds07-13710-7e *1: fpt-100p-m06 *2: fpt-100p-m20 (continued) pin no. pin name circuit type function qfp* 1 lqfp* 2 40 38 p52 g (cmos/h) general-purpose i/o port. an2 analog input pin (an2) for us e during a/d converter operation. sck3 uart3 serial clock i/o pin (sck3). this pin is enabled with t he uart3 clock output enabled. 41 39 p53 g (cmos/h) general-purpose i/o port. an3 analog input pin (an3) for us e during a/d converter operation. 43 41 p54 g (cmos/h) general-purpose i/o port. an4 analog input pin (an4) for us e during a/d converter operation. sin4 uart4 serial data input pin (sin4). when uart4 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. 44 42 p55 g (cmos/h) general-purpose i/o port. an5 analog input pin (an5) for us e during a/d converter operation. sot4 uart4 serial data output pin (sot4). this pin is enabled with the ua rt4 serial data output enabled. 45 43 p56 g (cmos/h) general-purpose i/o port. an6 analog input pin (an6) for us e during a/d converter operation. sck4 uart4 serial clock output pin (sck4). this pin is enabled with t he uart4 clock output enabled. 46 44 p57 g (cmos/h) general-purpose i/o port. an7 analog input pin (an7) for us e during a/d converter operation. 27 25 c ? 0.1 f capacitor coupling pin for regulating the power supply. 28 26 p71 f (cmos/h) general-purpose i/o port. 29 27 p72 f (cmos/h) general-purpose i/o port. 32 30 p73 h (cmos/h) general-purpose i/o port. this pin serves as a d/a output pin (da00) when the dae0 bit in the d/a control register (dacr) is ?1?. da00 d/a converter output 0 (da00) pin. 33 31 p74 h (cmos/h) general-purpose i/o port. this pin serves as a d/a output pin (da01) when the dae1 bit in the d/a control register (dacr) is ?1?. da01 d/a converter output 1 pin (da01). 47 45 p80 f (cmos/h) general-purpose i/o port. irq0 functions as external interru pt request input 0 pin (irq0).
mb90580c series ds07-13710-7e 13 *1: fpt-100p-m06 *2: fpt-100p-m20 (continued) pin no. pin name circuit type function qfp* 1 lqfp* 2 48 46 p81 f (cmos/h) general-purpose i/o port. irq1 functions as external interr upt request input 1 pin (irq1). 53 51 p82 f (cmos/h) general-purpose i/o port. irq2 functions as external interr upt request input 2 pin (irq2). 54 52 p83 f (cmos/h) general-purpose i/o port. irq3 functions as external interr upt request input 3 pin (irq3). 55 53 p84 f (cmos/h) general-purpose i/o port. irq4 functions as external interr upt request input 4 pin (irq4). 56 54 p85 f (cmos/h) general-purpose i/o port. irq5 functions as external interr upt request input 5 pin (irq5). 57 55 p86 f (cmos/h) general-purpose i/o port. irq6 functions as external interr upt request input 6 pin (irq6). 58 56 p87 f (cmos/h) general-purpose i/o port. irq7 functions as external interr upt request input 7 pin (irq7). 59 57 p60 d (cmos/h) general-purpose i/o port. a pull-up resistor can be assigned (rd60=?1?) by the pull-up resistor setting register (rdr6). [this pin is disabled with the output setting (ddr6 register: d60=?1?).] sin2 uart2 serial data input pin (sin2). when uart2 is operating for input , this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. 60 58 p61 d (cmos/h) general-purpose i/o port. a pull-up resistor can be assigned (rd61=?1?) by the pull-up resistor setting register (rdr6). [this pin is disabled with the output setting (ddr6 register: d61=?1?).] sot2 uart2 serial data output pin (sot2). this pin is enabled with the uart2 serial data output enabled. 61 59 p62 d (cmos/h) general-purpose i/o port. a pull-up resistor can be assigned (rd62=?1?) by the pull-up resistor setting register (rdr6). [this pin is disabled with the output setting (ddr6 register: d62=?1?).] sck2 uart2 serial clock i/o pin (sck2). this pin is enabled with the uart2 clock output enabled.
mb90580c series 14 ds07-13710-7e *1: fpt-100p-m06 *2: fpt-100p-m20 *3: n.c. pin on the mb90587c/ca. (continued) pin no. pin name circuit type function qfp* 1 lqfp* 2 62 60 p63 d (cmos/h) general-purpose i/o port. a pull-up resistor can be assigned (rd63=?1?) by the pull-up resis- tor setting register (rdr6). [this pin is disabled with the output set- ting (ddr6 register: d63=?1?).] ppg1 the pin serves as the ppg 1 output when ppgs are enabled. 63 61 p64 d (cmos/h) general-purpose i/o port. a pull-up resistor can be assigned (rd64=?1?) by the pull-up resis- tor setting register (rdr6). [this pin is disabled with the output set- ting (ddr6 register: d64=?1?).] ppg0 the pin serves as the ppg 0 output when ppgs are enabled. 64 62 p65 d (cmos/h) general-purpose i/o port. a pull-up resistor can be assigned (rd65=?1?) by the pull-up resis- tor setting register (rdr6). [this pin is disabled with the output set- ting (ddr6 register: d65=?1?).] ckot this pin serves as the ckot output during ckot operation. 65 63 tx* 3 i this pin serves as the iebus tm output. 66 64 rx* 3 j (cmos) this pin serves as the iebus tm input. 67 to 69 65 to 67 p90 to p92 f (cmos/h) general-purpose i/o port. tin0 to tin2 event input pins for reload timers 0, 1, and 2. during reload timer input, these inputs are used continuously and thus the output from any other function to the pins must be avoided unless used intentionally. in0 to in2 trigger inputs for input capture channels 0 to 2 70 68 p93 f (cmos/h) general-purpose i/o port. tot0 reload timer output pin. this fu nction is applied when the output for reload timer 0 is enabled. in3 trigger inputs for input capture channel 3. 71, 72 69, 70 p94, p95 f (cmos/h) general-purpose i/o port. tot1, tot2 reload timer output pins. this f unction is applied when the output for reload timer 1 and 2 are enabled. out0, out1 event output for channel 0 and 1 of the output compare 73 71 p96 f (cmos/h) general-purpose i/o port. pwc this pin serves as the pwc input with the pwc timer enabled.
mb90580c series ds07-13710-7e 15 (continued) *1: fpt-100p-m06 *2: fpt-100p-m20 pin no. pin name circuit type function qfp* 1 lqfp* 2 74 72 p97 f (cmos/h) general-purpose i/o port. pot this pin serves as the pwc output with the pwc timer enabled. 75, 76 73, 74 pa0, pa1 f (cmos/h) general-purpose i/o port. 78 76 pa2 f (cmos/h) general-purpose i/o port. 79 77 x1a a oscillation pin. leave the terminal open for the one clock system parts. 80 78 x0a a oscillation pin. pull-down the terminal externally for the one clock system parts. 34 32 av cc ? a/d converter power supply pin. 37 35 av ss ? a/d converter power supply pin. 35 33 avrh ? a/d converter external reference power supply pin. 36 34 avrl ? a/d converter external reference power supply pin. 30 28 dvrh ? d/a converter external reference power supply pin. 31 29 dv ss ? d/a converter power supply pin. 49 to 51 47 to 49 md0 to md2 c input pin for specifying the operation mode. connect these pins directly to vcc or vss. 23, 84 21, 82 v cc ? power supply (5 v) input pin. 11, 42, 81 9, 40, 79 v ss ? power supply (0 v) input pin.
mb90580c series 16 ds07-13710-7e i/o circuit type (continued) type circuit remarks a ? high-speed oscillation feedback resistance : approx. 1 m ? low-speed oscillation feedback resistance : approx. 10 m b ? hysteresis input with pull-up resistance : approx. 50 k c ? hysteresis input d ? incorporates pull-up resistor control (for input) ? cmos level output ? hysteresis input with standby control resistance : approx. 50 k x1, x1a x0, x0a hard,soft standby control clock input pull-up resistor control standby control signal
mb90580c series ds07-13710-7e 17 (continued) type circuit remarks e ? cmos level output ? hysteresis input with standby control ? incorporates open-drain control f ? cmos level output ? hysteresis input with standby control g ? cmos level output ? hysteresis input with standby control ? analog input standby control signal ? open-drain control signal standby control signal analog input standby control signal
mb90580c series 18 ds07-13710-7e (continued) type circuit remarks h ? cmos level output ? hysteresis input with standby control ? da output i ? cmos level output j ? cmos input with standby control da output standby control signal standby control signal
mb90580c series ds07-13710-7e 19 handling devices 1. preventing latch-up cmos ics may cause latch-up in the following situations: ? when a voltage higher than vcc or lower than vss is applied to input or output pins. ? when a voltage exceeding the ra ting is applied between vcc and vss. ? when avcc power is supplied prior to the vcc voltage. if latch-up occurs, the power supply current increases ra pidly, sometimes resulting in thermal breakdown of the device. use meticulous ca re not to let it occur. for the same reason, also be careful not to let the anal og power-supply voltage exceed the digital power-supply voltage. 2. handling unused input pins unused input pins left open may cause abnormal operat ion, or latch-up leading to permanent damage. unused input pins should be pulled up or pulled down through at least 2 k resistance. unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. 3. treatment of the tx and rx pins with the iebus tm unused when the iebus is not used, connect a pull-down resistor to the tx pin and a pull-down/pull-up resistor to the rx pin. 4. use of the external clock when the device uses an external clock, drive only the x0 pin while leaving the x1 pin open (see the illustration below). 5. power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of a same potential ar e internally connected in the device to avoid abnormal operations including latch-up. however, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. x0 x1 mb90580c series open
mb90580c series 20 ds07-13710-7e it is recommended to provide a bypass capacitor of around 0.1 f between v cc and v ss pin near the device. 6. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crys tal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of osc illation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with an grand area for stabilizing the operation. 7. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , av ss , avrh, avrl) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d conv erter supply and analog inputs. in this case, make sure that the voltage of avrh dose not exceed av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable). 8. connection of unused pins of a/d converter connect unused pin of a/d converter to av cc = v cc , av ss = avrh = avrl = v ss . 9. connection of unused pins of d/a converter connect unused pin of d/a converter to dvrh = v ss , dv ss = v ss . 10. n.c. pin the n.c. (internally connecte d) pin must be opened for use. 11. notes on energization to prevent the internal regulator circ uit from malfunctioning, set the volta ge rise time during energization at 50 s or more (0.2 v to 2.7 v). 12. use of the sub-clock use the one clock system parts when the sub-clock is not used. connected the oscillator under 32 khz to the both terminals xa0 and x1a for the two clocks system par ts. pull-down the terminal x0a and leave the terminal x0a open for the one clock system parts. v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90580c series
mb90580c series ds07-13710-7e 21 13. indeterminate outputs from ports 0 and 1 the outputs from ports 0 and 1 become indeterminate du ring a power-on reset after the power is turned on. pay attention to the port output timing shown as follow. 14. initialization in the device, there are internal registers which are initializ ed only by a power-on reset. to initialize these registers turning on the power again. 15. return from standby state if the power-supply voltage goes below the standby ram holding voltage in the standby state, the device may fail to return from the standby state. in this case, reset the device via the exte rnal reset pin to return to the normal state. 16. precautions for use of ?div a, ri,? and ?divw a, rwi? instructions the signed multiplication-division instructions ?div a, ri,? and ?divw a, rwi? shou ld be used when the corre- sponding bank registers (dtb, adb, usb, ssb) are set to value ?00h.? if the corresponding bank registers (dtb, adb, usb, ssb) are set to a value other than ?00h,? then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 17. precautions for use of realos extended intelligent i/o service (ei 2 os) cannot be used, when realos is used. v cc (power-supply pin) ponr (power-on reset) signal rst (external asynchro nous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operation clock a) signal kb (internal operation clock b) signal port (port output) signal period of indeterminate power-on reset* 1 oscillation settling time* 2 *1: power-on reset time: period of ?clock frequency x 2 17 ? (clock frequency of 16 mhz: 8.192 ms) *2: oscillation settling time: period of ?clock frequency x 2 18 ? (clock frequency of 16 mhz: 16.384 ms)
mb90580c series 22 ds07-13710-7e 18. caution on pll clock mode if the pll clock mode is selected, the microcontroller atte mpt to be working with the self-oscillating circuit even when there is no external oscillator or external clock in put is stopped. performance of this operation, however, cannot be guaranteed.
mb90580c series ds07-13710-7e 23 block diagram x0, x1 x0a, x1a rst hst 6 8 3 3 8 8 3 p00 to p07/ ad00 to ad07 p10 to p17/ ad08 to ad15 p20 to p27/ a16 to a23 p30/ale p31/rd p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk p47 sin0, sot0, sck0/ p40 to p42 3 8 8 sin1, sot1, sck1/ p43 to p45 p90 to p92/ tin0 to tin2/ in0 to in2 2 p94, p95/ tot1, tot2/ out0, out1 2 2 p63, p64/ ppg1, ppg0 3 sin2, sot2, sck2/ p60 to p62 8 p80 to p87/ irq0 to irq7 2 p71, p72 2 p73, p74 /da00, da01 p93/ tot0/ in3 pa0 to pa2 p96/pwc p97/pot p65/ckot dvrh dv ss adtg / p46 av cc avrh, avrl av ss sin3, sot3, sck3/ p50 to p52/ an0 to an2 p53/an3, p57/an7 sin4, sot4, sck4/ p54 to p56/ an4 to an6 tx rx rom uart 2 ch uart 1 ch 8 / 16 ppg 1 ch uart 2 ch ram * other pins md2 to md0 c,v cc ,v ss 3 3 2 clock control circuit cmos i/o port 0 cmos i/o port 1 cmos i/o port 2 cmos i/o port 3 prescaler 2 ch a/d converter (8/10 bit) interrupt controller cmos i/o port a cmos i/o port 9 cmos i/o port 8 cmos i/o port 7 external interrupt d/a converter (8 bit) 2 ch evaluation device (mb90v580b) this chip has no internal rom. internal ram is 6 kbytes. internal resources are common. the package is pga-256c-a02. iebus tm controller prescaler 2 ch cmos i/o port 6 cmos i/o port 5 f 2 mc-16lx bus i/o timer 16 bit icu 4 ch 16 bit ocu 2 ch 16 bit free run timer 16 bit reload timer 3 ch noise filter pwc timer 16 bit 1 ch prescaler 1 ch p00 to 07 (8 channels): provi ded with a register available as an input pull-up resistor. p10 to 17(8 channels): provided with a regi ster available as an input pull-up resistor. p60 to 65(6 channels): provided with a regi ster available as an input pull-up resistor. p40 to 47 (8 channels): provided with a register available as an open drain. *: the mb90587c/ca has no iebus tm controller. the tx and rx pins are n.c. pins. clock monitor cpu core of f 2 mc-16lx family cmos i/o port 4
mb90580c series 24 ds07-13710-7e memory map note: the rom data of bank ff is refl ected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit is assigned to the same address, enabling reference of the table on the rom without stating ?far?. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed actually. since the rom area of the ff bank exceeds 48 kbytes, the whole area cannot be reflecte d in the image for the 00 b ank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 00400h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . ram ram ram ffffff h fc0000 h 010000 h 004000 h 002000 h 000100 h 0000c0 h 000000 h rom area rom area rom area (image of bank ff) rom area (image of bank ff) register peripheral peripheral peripheral single chip mode a mirror function is supported int ernal rom external bus mode a mirror function is supported external rom external bus mode : internal : external : inhibited area parts no. address#1 address#2 address#3 mb90583c/ca fe0000 h 004000 h 001900 h mb90f583c/ca fe0000 h 004000 h 001900 h mb90f584c/ca fc0000 h 004000 h 001900 h mb90587c/ca ff0000 h 004000 h 001100 h mb90v580b (fe0000 h ) 004000 h 001900 h address#1 address#2 address#3 register register
mb90580c series ds07-13710-7e 25 f 2 mc-16lx cpu programming model ? dedicated registers ah al usp ssp ps pc dpr pcb dtb usb ssb adb 8 bit 16 bit 32 bit : accumulator (a) dual 16-bit register used for storing results of calculation etc. the two 16-bit registers can be combined to be used as a 32-bit register. : user stack pointer (usp) the 16-bit pointer indicating a user stack address. : system stack pointer (ssp) the 16-bit pointer indicating the status of the system stack address. : processor status (ps) the 16-bit register indicating the system status. : program counter (pc) the 16-bit register indicating storing location of the current instruction code. : direct page register (dpr) the 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : program bank register (pcb) the 8-bit register indicating the program space. : data bank register (dtb) the 8-bit register indicating the data space. : user stack bank register (usb) the 8-bit register indicating the user stack space. : system stack bank register (ssb) the 8-bit register indicating the system stack space. : additional data bank register (adb) the 8-bit register indicating the additional data space.
mb90580c series 26 ds07-13710-7e ? general-purpose registers ? processor status (ps) r7 r6 r5 r4 r3 r2 r1 rw3 rw2 rw1 rw0 16 bit r0 rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 000180 h + (rp 10 h ) maximum of 32 banks bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 ilm rp ccr bit 3 bit 2 bit 1 bit 0 ilm2 ps ilm1 ilm0 b4 b3 b2 b1 b0 ? istnzvc 00000000 ? 0 1xxxxx initial value ? x : unused : undefined
mb90580c series ds07-13710-7e 27 i/o map (continued) address register name abbreviated register name read/write resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 1 1 1 1 1 1 1 1 b 06 h port 6 data register pdr6 r/w port 6 ? ? xxxxxx b 07 h port 7 data register pdr7 r/w port 7 ? ? ? xxxx ? b 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 0a h port a data register pdra r/w port a ? ? ? ? ? xxx b 0b h to 0f h (disabled) 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 b 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 b 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 b 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 b 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 b 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 b 16 h port 6 direction register ddr6 r/w port 6 ? ? 0 0 0 0 0 0 0 b 17 h port 7 direction register ddr7 r/w port 7 ? ? ? 0 0 0 0 ? b 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 b 19 h port 9 direction register ddr9 r/w port 9 0 0 0 0 0 0 0 0 b 1a h port a direction register ddra r/w port a ? ? ? ? ? 0 0 0 b 1b h port 4 output pin register odr4 r/w port 4 0 0 0 0 0 0 0 0 b 1c h port 5 analog input enable register ader r/w port 4, a/d 1 1 1 1 1 1 1 1 b 1d h to 1f h (disabled) 20 h serial mode register 0 smr0 r/w uart0 0 0 0 0 0 0 0 0 b 21 h serial control register 0 scr0 r/w 0 0 0 0 0 1 0 0 b 22 h serial input data register 0/ serial output data register 0 sidr0/ sodr0 r/w xxxxxxxx b 23 h serial status register 0 ssr0 r/w 0 0 0 0 1 ? 0 0 b
mb90580c series 28 ds07-13710-7e (continued) address register name abbreviated register name read/ write resource name initial value 24 h serial mode register 1 smr1 r/w uart1 0 0 0 0 0 0 0 0 b 25 h serial control register 1 scr1 r/w 0 0 0 0 0 1 0 0 b 26 h serial input data register 1/ serial output data register 1 sidr1/ sodr1 r/w xxxxxxxx b 27 h serial status register 1 ssr1 r/w 0 0 0 0 1 ? 0 0 b 28 h serial mode register 2 smr2 r/w uart2 0 0 0 0 0 0 0 0 b 29 h serial control register 2 scr2 r/w 0 0 0 0 0 1 0 0 b 2a h serial input data register 2/ serial output data register 2 sidr2/ sodr2 r/w xxxxxxxx b 2b h serial status register 2 ssr2 r/w 0 0 0 0 1 ? 0 0 b 2c h clock division control register 0 cdcr0 r/w communications prescaler 0 0 ? ? ? 1 1 1 1 b 2d h (disabled) 2e h clock division control register 1 cdcr1 r/w communications prescaler 1 0 ? ? ? 1 1 1 1 b 2f h (disabled) 30 h dtp/interrupt enable register enir r/w dtp/external interrupt 0 0 0 0 0 0 0 0 b 31 h dtp/interrupt factor register eirr r/w xxxxxxxx b 32 h request level setting register lower elvr r/w 0 0 0 0 0 0 0 0 b 33 h request level setting register upper 0 0 0 0 0 0 0 0 b 34 h clock division control register 2 cdcr2 r/w communications prescaler 2 0 ? ? ? 1 1 1 1 b 35 h (disabled) 36 h control status register lower adcs1 r/w a/d converter 0 0 0 0 0 0 0 0 b 37 h control status register upper adcs2 r/w 0 0 0 0 0 0 0 0 b 38 h data register lower adcr1 r xxxxxxxx b 39 h data register upper adcr2 r or w 0 0 0 0 1 ? xx b 3a h d/a converter data register 0 dat0 r/w d/a converter 0 0 0 0 0 0 0 0 b 3b h d/a converter data register 1 dat1 r/w 0 0 0 0 0 0 0 0 b 3c h d/a control register 0 dacr0 r/w ? ? ? ? ? ? ? 0 b 3d h d/a control register 1 dacr1 r/w ? ? ? ? ? ? ? 0 b 3e h clock output enable register clkr r/w clock monitor function ? ? ? ? 0 0 0 0 b 3f h (disabled)
mb90580c series ds07-13710-7e 29 (continued) address register name abbreviated register name read/ write resource name initial value 40 h reload register l (ch.0) prll0 r/w 8/16 bit ppg0/1 xxxxxxxx b 41 h reload register h (ch.0) prlh0 r/w xxxxxxxx b 42 h reload register l (ch.1) prll1 r/w xxxxxxxx b 43 h reload register h (ch.1) prlh1 r/w xxxxxxxx b 44 h ppg0 operating mode control register ppgc0 r/w 0 x 0 0 0 x x 1 b 45 h ppg1 operating mode control register ppgc1 r/w 0 x 0 0 0 0 0 1 b 46 h ppg0 and 1 operating output control registers ppgoe r/w 0 0 0 0 0 0 0 0 b 47 h (disabled) 48 h timer control status register lower tmcsr0 r/w 16 bit reload timer 0 0 0 0 0 0 0 0 0 b 49 h timer control status register upper ? ? ? ? 0 0 0 0 b 4a h 16 bit timer register lower/ 16 bit reload register lower tmr0/ tmrlr0 r/w xxxxxxxx b 4b h 16 bit timer register upper/ 16 bit reload register upper xxxxxxxx b 4c h timer control status register lower tmcsr1 r/w 16 bit reload timer 1 0 0 0 0 0 0 0 0 b 4d h timer control status register upper ? ? ? ? 0 0 0 0 b 4e h 16bit timer register lower/ 16 bit reload register lower tmr1/ tmrlr1 r/w xxxxxxxx b 4f h 16 bit timer register upper/ 16 bit reload register upper xxxxxxxx b 50 h timer control status register lower tmcsr2 r/w 16 bit reload timer 2 0 0 0 0 0 0 0 0 b 51 h timer control status register upper ? ? ? ? 0 0 0 0 b 52 h 16 bit timer register lower/ 16 bit reload register lower tmr2/ tmrlr2 r/w xxxxxxxx b 53 h 16 bit timer register upper/ 16 bit reload register upper xxxxxxxx b 54 h pwc control status register lower pwcsr r/w or r 16 bit pwc timer 0 0 0 0 0 0 0 0 b 55 h pwc control status register upper 0 0 0 0 0 0 0 0 b 56 h pwc data buffer register lower pwcr r/w xxxxxxxx b 57 h pwc data buffer register upper xxxxxxxx b 58 h divide ratio control register divr r/w ? ? ? ? ? ? 0 0 b 59 h (disabled)
mb90580c series 30 ds07-13710-7e (continued) address register name abbreviated register name read/write resource name initial value 5a h compare register lower occp0 r/w output compare (ch.0) xxxxxxxx b 5b h compare register upper xxxxxxxx b 5c h compare register lower occp1 r/w output compare (ch.1) xxxxxxxx b 5d h compare register upper xxxxxxxx b 5e h compare control status register 0 ocs0 r/w output compare (ch.0) 0 0 0 0 ? ? 0 0 b 5f h compare control status register 1 ocs1 r/w output compare (ch.1) ? ? ? 0 0 0 0 0 b 60 h input capture register lower ipcp0 r input capture (ch.0) xxxxxxxx b 61 h input capture register upper xxxxxxxx b 62 h input capture register lower ipcp1 r input capture (ch.1) xxxxxxxx b 63 h input capture register upper xxxxxxxx b 64 h input capture register lower ipcp2 r input capture (ch.2) xxxxxxxx b 65 h input capture register upper xxxxxxxx b 66 h input capture register lower ipcp3 r input capture (ch.3) xxxxxxxx b 67 h input capture register upper xxxxxxxx b 68 h input capture control status register 01 ics01 r/w input capture (ch.0, ch.1) 0 0 0 0 0 0 0 0 b 69 h (disabled) 6a h input capture control status register 23 ics23 r/w input capture (ch.2, ch.3) 0 0 0 0 0 0 0 0 b 6b h (disabled) 6c h timer data register lower tcdtl r/w free-run timer 0 0 0 0 0 0 0 0 b 6d h timer data register upper tcdth r/w 0 0 0 0 0 0 0 0 b 6e h timer control status register tccs r/w 0 0 0 0 0 0 0 0 b 6f h rom mirroring function selection register romm w rom mirror function ? ? ? ? ? ? ? 1 b 70 h local-office address setting register l mawl r/w iebus tm controller xxxxxxxx b 71 h local-office address setting register h mawh r/w xxxxxxxx b 72 h slave address setting register l sawl r/w xxxxxxxx b 73 h slave address setting register h sawh r/w xxxxxxxx b 74 h message length bit setting register dewr r/w 0 0 0 0 0 0 0 0 b 75 h broadcast control bit setting register dcwr r/w 0 0 0 0 0 0 0 0 b
mb90580c series ds07-13710-7e 31 (continued) address register name abbreviated register name read/write resource name initial value 76 h command register l cmrl r/w iebus tm controller 1 1 0 0 0 0 0 0 b 77 h command register h cmrh r/w 0 0 0 0 0 0 0 x b 78 h status register l strl r 0 0 1 1 xxxx b 79 h status register h strh r/w or r 0 0 xx 0 0 0 0 b 7a h lock read register l lrrl r xxxxxxxx b 7b h lock read register h lrrh r/w or r 1 1 1 0 xxxx b 7c h master address read register l marl r xxxxxxxx b 7d h master address read register h marh r 1 1 1 1 xxxx b 7e h message length bit read register derr r xxxxxxxx b 7f h broadcast control bit read register dcrr r 0 0 0 xxxxx b 80 h write data buffer wdb w xxxxxxxx b 81 h read data buffer rdb r xxxxxxxx b 82 h serial mode register 3 smr3 r/w uart3 0 0 0 0 0 0 0 0 b 83 h serial control register 3 scr3 r/w 0 0 0 0 0 1 0 0 b 84 h serial input register 3/ serial output register 3 sidr3/ sodr3 r/w xxxxxxxx b 85 h serial status register 3 ssr3 r/w 0 0 0 0 1 ? 0 0 b 86 h pwc noise filter register rncr r/w pwc noise filter ? ? ? ? ? 0 0 0 b 87 h clock division control register 3 cdcr3 r/w communications prescaler 3 0 ? ? ? 1 1 1 1 b 88 h serial mode register 4 smr4 r/w uart4 0 0 0 0 0 0 0 0 b 89 h serial control register 4 scr4 r/w 0 0 0 0 0 1 0 0 b 8a h serial input register 4/ serial output register 4 sidr4/ sodr4 r/w xxxxxxxx b 8b h serial status register 4 ssr4 r/w 0 0 0 0 1 ? 0 0 b 8c h port 0 input pull-up resistor setup register rdr0 r/w port 0 0 0 0 0 0 0 0 0 b 8d h port 1 input pull-up resistor setup register rdr1 r/w port 1 0 0 0 0 0 0 0 0 b 8e h port 6 input pull-up resistor setup register rdr6 r/w port 6 ? ? 0 0 0 0 0 0 b 8f h clock division control register 4 cdcr4 r/w communications prescaler 4 0 ? ? ? 1 1 1 1 b 90 h to 9d h (disabled)
mb90580c series 32 ds07-13710-7e (continued) address register name abbreviated register name read/ write resource name initial value 9e h program address detection control/ status register pacsr r/w address match detection function 0 0 0 0 0 0 0 0 b 9f h delayed interrupt generation/release register dirr r/w delayed interrupt generation module ? ? ? ? ? ? ? 0 b a0 h low-power consumption mode control register lpmcr r/w or w low-power consumption mode 0 0 0 1 1 0 0 ? b a1 h clock selection register ckscr r/w or r 1 1 1 1 1 1 0 0 b a2 h to a4 h (disabled) a5 h auto-ready function selection register arsr w external bus pin control circuit 0 0 1 1 ? ? 0 0 b a6 h external address output control register hacr w 0 0 0 0 0 0 0 0 b a7 h bus control signal selection register ecsr w 0 0 0 0 0 0 0 ? b a8 h watch dog timer control register wdtc r or w watch dog timer xxxxx 1 1 1 b a9 h time-base timer control register tbtc r/w, w timebase timer 1 ? ? 0 0 1 0 0 b aa h watch timer control register wtc r/w or r watch timer 1 x 0 0 0 0 0 0 b ab h to ad h (disabled) ae h flash memory control status register fmcs r/w or r or w flash interface 0 0 0 x 0 0 0 0 b af h (disabled) b0 h interrupt control register 00 icr00 r/w interrupt controller 0 0 0 0 0 1 1 1 b b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 b b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 b b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 b ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 b bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 b bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 b bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 b be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 b bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 b
mb90580c series ds07-13710-7e 33 (continued) ? explanation of initial values ?0? : initial value?0? / ?1? : initial value?1? / ?x? : undefined / ? ? ? : undefined (not used) ? the addresses following 00ff h are reserved. no external bus access signal is generated. ? boundary # h between the ram area and the reserved area varies with the product model. note: for bits that is initialized by an reset operation, the initial value set by t he reset operation is listed as an initial value. note that the values are different from r eading results. for lpmcr/ckscr/wdtc, there are cases where initialization is performed or not performed, de pending on the types of the reset. however initial value for resets that initializes the value are listed. address register name abbreviated register name read/write resource name initial value c0 h to ff h (external area) 100 h to # h (ram area) # h to 1fef h (reserved area) 1ff0 h program address detection register 0 (lower) padr0 r/w address match detection function xxxxxxxx b 1ff1 h program address detection register 0 (middle) r/w xxxxxxxx b 1ff2 h program address detection register 0 (upper) r/w xxxxxxxx b 1ff3 h program address detection register 1 (lower) padr1 r/w xxxxxxxx b 1ff4 h program address detection register 1 (middle) r/w xxxxxxxx b 1ff5 h program address detection register 1 (upper) r/w xxxxxxxx b 1ff6 h to 1fff h (reserved area)
mb90580c series 34 ds07-13710-7e interrupt factors, interrupt vectors, interrupt control register : indicates that the interrupt request flag is cleared by the ei 2 os interrupt clear signal (stop request present). : indicates that the interrupt request flag is cleared by the ei 2 os interrupt clear signal. : indicates that the interrupt re quest flag is not cleared by the ei 2 os interrupt clear signal. interrupt source ei 2 os support interrupt vector interrupt control register priority no. address icr address reset #08 ffffdc h ?? high int9 instruction #09 ffffd8 h ?? exception #10 ffffd4 h ?? a/d converter #11 ffffd0 h icr00 0000b0 h timebase timer #12 ffffcc h dtp0 (external interrupt #0) /uart3 reception complete #13 ffffc8 h icr01 0000b1 h dtp1 (external interrupt #1) /uart4 reception complete #14 ffffc4 h dtp2 (external interrupt #2) /uart3 transmission complete #15 ffffc0 h icr02 0000b2 h dtp3 (external interrupt #3) /uart4 transmission complete #16 ffffbc h dtp4 to 7 (external interrupt #4 to #7) #17 ffffb8 h icr03 0000b3 h output compare (ch.1) match (i/o timer) #18 ffffb4 h uart2 reception complete #19 ffffb0 h icr04 0000b4 h uart1 reception complete #20 ffffac h input capture (ch.3) include (i/o timer) #21 ffffa8 h icr05 0000b5 h input capture (ch.2) include (i/o timer) #22 ffffa4 h input capture (ch.1) include (i/o timer) #23 ffffa0 h icr06 0000b6 h input capture (ch.0) include (i/o timer) #24 ffff9c h 8/16 bit ppg0 counter borrow #25 ffff98 h icr07 0000b7 h 16 bit reload timer 2 to 0 #26 ffff94 h watch prescaler #27 ffff90 h icr08 0000b8 h output compare (ch.0) match (i/o timer) #28 ffff8c h uart2 transmission complete #29 ffff88 h icr09 0000b9 h pwc timer measurement complete / over flow #30 ffff84 h uart1 transmission complete #31 ffff80 h icr10 0000ba h 16-bit free run timer ( i/o timer ) over flow #32 ffff7c h uart0 transmission complete #33 ffff78 h icr11 0000bb h 8/16 bit ppg1 counter borrow #34 ffff74 h iebus reception complete #35 ffff70 h icr12 0000bc h iebus transmission start #37 ffff68 h icr13 0000bd h uart0 reception complete #39 ffff60 h icr14 0000be h flash memory status #41 ffff58 h icr15 0000bf h delayed interrupt #42 ffff54 h low
mb90580c series ds07-13710-7e 35 peripheral resources 1. i/o ports (1) outline of i/o ports when a data register serving for control ou tput is read, the data output from it as a control output is read regardless of the value in the direction register. note that, if a read modify write instruction (such as a bit set instruction) is used to preset output data in the data register when c hanging its setting from input to output, the data read is not the data register latched valu e but the input data from the pin. ports 0 to 4 and 6 to a are input/output ports which serve as inputs when the direction register value is ?0? or as outputs when the value is ?1?. on the mb90580c series, ports 0 to 3 also serve as exter nal bus pins. when the device is used in external bus mode, therefore, these ports are restricted on use. ports 2 and 3 can be used as ports even in external bus mode depending on the setting of the corresponding function select bit. (2) register configuration (continued) ? port 0 data register ( pdr0 ) bit address : 000000 h access initial value ? port 1 data register ( pdr1 ) bit address : 000001 h access initial value ? port 2 data register ( pdr2 ) bit address : 000002 h access initial value ? port 3 data register ( pdr3 ) bit address : 000003 h access initial value ? port 4 data register ( pdr4 ) bit address : 000004 h access initial value (pdr1) p07 p06 p05 p04 p03 p02 p01 p00 76543210 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 8 (pdr0) p17 p16 p15 p14 p13 p12 p11 p10 15 14 13 12 11 10 9 8 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 70 (pdr3) p27 p26 p25 p24 p23 p22 p21 p20 76543210 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 8 (pdr2) p37 p36 p35 p34 p33 p32 p31 p30 15 14 13 12 11 10 9 8 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 70 (pdr5) p47 p46 p45 p44 p43 p42 p41 p40 76543210 (r/w) (x) (rw) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 8
mb90580c series 36 ds07-13710-7e (continued) ? port 5 data register ( pdr5 ) bit address : 000005 h access initial value ? port 6 data register ( pdr6 ) bit address : 000006 h access initial value ? port 7 data register ( pdr7 ) bit address : 000007 h access initial value ? port 8 data register ( pdr8 ) bit address : 000008 h access initial value ? port 9 data register ( pdr9 ) bit address : 000009 h access initial value ? port a data register ( pdra ) bit address : 00000a h access initial value ? port 0 direction register (ddr0) bit address : 000010 h access initial value (pdr4) p57 p56 p55 p54 p53 p52 p51 p50 15 14 13 12 11 10 9 8 (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) 70 (pdr7) ?? p65 p64 p63 p62 p61 p60 76543210 (?) (?) (?) (?) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 8 (pdr6) ??? p74 p73 p72 p71 ? 15 14 13 12 11 10 9 8 (?) (?) (?) (?) (?) (?) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (?) (?) 70 (pdr9) p87 p86 p85 p84 p83 p82 p81 p80 76543210 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 8 (pdr8) p97 p96 p95 p94 p93 p92 p91 p90 15 14 13 12 11 10 9 8 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 70 ????? pa2 pa1 pa0 76543210 (?) (?) (?) (?) (?) (?) (?) (?) (?) (?) (r/w) (x) (r/w) (x) (r/w) (x) 15 8 (disabled) (ddr1) d07 d06 d05 d04 d03 d02 d01 d00 76543210 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8
mb90580c series ds07-13710-7e 37 (continued) ? port 1 direction register ( ddr1 ) bit address : 000011 h access initial value ? port 2 direction register ( ddr2 ) bit address : 000012 h access initial value ? port 3 direction register ( ddr3 ) bit address : 000013 h access initial value ? port 4 direction register ( ddr4 ) bit address : 000014 h access initial value ? port 5 direction register ( ddr5 ) bit address : 000015 h access initial value ? port 6 direction register ( ddr6 ) bit address : 000016 h access initial value ? port 7 direction register ( ddr7 ) bit address : 000017 h access initial value (ddr0) d17 d16 d15 d14 d13 d12 d11 d10 15 14 13 12 11 10 9 8 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 70 (ddr3) d27 d26 d25 d24 d23 d22 d21 d20 76543210 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 (ddr2) d37 p36 p35 p34 p33 p32 p31 p30 15 14 13 12 11 10 9 8 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 70 (ddr5) d47 d46 d45 d44 d43 d42 d41 d40 76543210 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 (ddr4) d57 d56 d55 d54 d53 d52 d51 d50 15 14 13 12 11 10 9 8 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 70 (ddr7) ?? d65 d64 d63 d62 d61 d60 76543210 (?) (?) (?) (?) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 ? (ddr6) ??? d74 d73 d72 d71 15 14 13 12 11 10 9 8 (?) (?) (?) (?) (?) (?) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (?) (?) 70
mb90580c series 38 ds07-13710-7e (continued) ? port 8 direction register ( ddr8 ) bit address : 000018 h access initial value ? port 9 direction register ( ddr9 ) bit address : 000019 h access initial value ? port a direction register ( ddra ) bit address : 00001a h access initial value ? port 4 output pin register ( odr4 ) bit address : 00001b h access initial value ? port 5 analog input enable register ( ader ) bit address : 00001c h access initial value ? port 0 input pull-up resistor setup register ( rdr0 ) bit address : 00008c h access initial value ? port 1 input pull-up resistor setup register ( rdr1 ) bit address : 00008d h access initial value (ddr9) d87 d86 d85 d84 d83 d82 d81 d80 76543210 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 (rdr1) rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 76543210 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 (ddr8) d97 d96 d95 d94 d93 d92 d91 d90 15 14 13 12 11 10 9 8 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 70 (odr4) ????? da2 da1 da0 76543210 (?) (?) (?) (?) (?) (?) (?) (?) (?) (?) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 (ddra) od47 od46 od45 od44 od43 od42 od41 od40 15 14 13 12 11 10 9 8 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 70 ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 76543210 (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) 15 8 (rdr1) rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 76543210 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8 (rdr0) rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 15 14 13 12 11 10 9 8 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 70
mb90580c series ds07-13710-7e 39 (continued) ? port 6 input pull-up resistor setup register ( rdr6 ) bit address : 00008e h access initial value (cdcr4) ?? rd65 rd64 rd63 rd62 rd61 rd60 76543210 (?) (?) (?) (?) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 8
mb90580c series 40 ds07-13710-7e (3) block diagram ? input/output port ? input pull-up resi stor setup register data register read data register write direction register write direction register read data register direction register pin data register direction register input pull-up resistor setup register pull-up resistor ( about 50 k ) port i/o internal data bus bus
mb90580c series ds07-13710-7e 41 ? output pin register data register direction register pin register port i/o bus
mb90580c series 42 ds07-13710-7e 2. timebase timer the time-base timer consists of a 18-b it timer and an interval interrupt control circuit. note that the time-base timer uses the oscillation clock regardless of the setting of the mcs bit in the ckscr. (1) register configuration (2) block diagram ? timebase timer control register bit15 1413121110 9 8 address : 0000a9 h reserved ?? tbie tbof tbr tbc1 tbc0 tbtc access (r/w) ( ? ) ( ? ) (r/w) (r/w) (w) (r/w) (r/w) initial value (1) ( ? ) ( ? ) (0) (0) (1) (0) (0) tbtc ponr stbr wrst erst srst tbc0 tbr tbie tbof tbc1 wt1 wt0 wte wtc wdcs sce wtc2 wtc1 wtc0 wtr wtie wtof wdtc wdtc and clr of clr 2 12 2 14 2 16 2 19 tbtres 2 9 2 10 2 11 2 12 2 13 2 14 2 15 wtres 2 11 2 13 2 15 2 18 2 10 2 13 2 14 2 15 qr s and q r s and q r s main clock clock input time-base timer watchdog reset generator watch timer clock input to wdgrst internal reset generator from power-on reset generator sub clock from rst bit in stbyc register from rst pin from hardware standby control circuit time-base interrupt clock interrupt selector selector selector 2-bit counter f 2 mc-16lx bus
mb90580c series ds07-13710-7e 43 3. watchdog timer the watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit time-base timer as the clock source, a control register, and a watchdog reset control section. (1) register configuration (2) block diagram ? watchdog timer control register bit 76543210 address : 0000a8 h ponr stbr wrst erst srst wte wt1 wt0 wdtc access (r) (r) (r) (r) (r) (w) (w) (w) initial value (x) (x) (x) (x) (x) (1) (1) (1) tbtc ponr stbr wrst erst srst tbc0 tbr tbie tbof tbc1 wt1 wt0 wte wtc wdcs sce wtc2 wtc1 wtc0 wtr wtie wtof wdtc wdtc and clr of clr 2 12 2 14 2 16 2 19 tbtres 2 9 2 10 2 11 2 12 2 13 2 14 2 15 wtres 2 11 2 13 2 15 2 18 2 10 2 13 2 14 2 15 qr s and q r s and q r s time-base interrupt watch interrupt selector selector selector main clock clock input time-base timer watchdog reset generator 2-bit counter watch timer clock input to wdgrst internal reset generator from power-on reset generator sub clock from rst bit in stbyc register from rst pin f 2 mc-16lx bus from hardware standby control circuit
mb90580c series 44 ds07-13710-7e 4. watch timer the watch timer has the functions of a watchdog timer clock source, a sub clock oscillation settling time wait timer, and of a periodically inte rrupt generating interval timer. (1) register configuration (2) block diagram ? watch timer control register bit 7 6543210 address : 0000aa h wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 wtc access (r/w) (r) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (1) (x) (0) (0) (0) (0) (0) (0) tbtc ponr stbr wrst erst srst tbc0 tbr tbie tbof tbc1 wt1 wt0 wte wtc wdcs sce wtc2 wtc1 wtc0 wtr wtie wtof wdtc wdtc and clr of clr 2 12 2 14 2 16 2 19 tbtres 2 9 2 10 2 11 2 12 2 13 2 14 2 15 wtres 2 11 2 13 2 15 2 18 2 10 2 13 2 14 2 15 qr s and q r s and q r s time-base interrupt watch interrupt selector selector selector main clock clock input time-base timer watchdog reset generator 2-bit counter watch timer clock input to wdgrst internal reset generator from power-on reset generator sub clock from rst bit in stbyc register from rst pin f 2 mc-16lx bus from hardware standby control circuit
mb90580c series ds07-13710-7e 45 5. external memory access (external bus pin control circuit) the external bus pin control circuit controls external bus pins used to expand the address/data buses of the cpu outside. (1) register configuration ( 2 ) block diagram ? automatic ready functi on selection register bit address : 0000a5 h access initial value ? external address output control register bit address : 0000a6 h access initial value ? bus control signal selection register bit address : 0000a7 h access initial value arsr ior1 ior0 hmr1 hmr0 ?? lmr1 lmr0 15 14 13 12 11 10 9 8 (w) (0) (w) (0) (w) (1) (w) (1) (?) (?) (?) (?) (w) (0) (w) (0) hacr e23 e22 e21 e20 e19 e18 e17 e16 76543210 (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) ecsr cke rye hde iobs hmbs wre lmbs ? 15 14 13 12 11 10 9 8 (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (?) (?) p0 rb p0 p1 p2 p3 p3 p0 data access control p0 direction data control address control access control
mb90580c series 46 ds07-13710-7e 6. pwc timer the pwc (pulse width count) timer is a 16-bit multifunc tion up-counter with reload timer functions and input- signal pulse-width count functions as well. the pwc timer consists of a 16-bit counter, a input pul se divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. (1) features of the pwc timer the pwc timer has the following features: ? timer functions generates an interrupt req uest at set time intervals. outputs pulse signals synchronized with the timer cycle. selects the counter clock from among three internal clocks. ? pulse-width count functions counts the time between external pulse input events. selects the counter clock from among three internal clocks. count mode ? h pulse width (rising edge to falling edge)/l pulse width (falling edge to rising edge) ? rising-edge cycle (rising edge to falling edge)/f alling-edge cycle (falling edge to rising edge) ? count between edges (rising or fa lling edge to falling or rising edge) capable of counting cycles by dividing input pulses by 2 2 , 2 4 , 2 6 , 2 8 using an 8-bit input divider. generates an interrupt request upon the completion of count operation. selects single or consecutive count operation.
mb90580c series ds07-13710-7e 47 (2) register configuration ? pwc control status register upper bit151413121110 9 8 address : 000055 h strt stop edir edie ovir ovie err pout pwcsr upper access (r/w) (r/w) (r) (r/w ) (r/w) (r/w) (r) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? pwc control status register lower bit76543210 address : 000054 h cks1 cks0 reservedreserved s/c mod2 mod1 mod0 pwcsr lower access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? pwc data buffer register upper bit151413121110 9 8 address : 000057 h pwcr upper access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? pwc data buffer register lower bit76543210 address : 000056 h pwcr lower access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? divide ratio control register bit76543210 address : 000058 h ?????? div1 div0 divr access ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) (r/w) initial value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (0) (0) ? pwc noise filter register bit76543210 address : 000086 h ????? sw1 sw0 en rncr access ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) (r/w) (r/w) initial value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (0) (0) (0)
mb90580c series 48 ds07-13710-7e (3) block diagram err pwcr 16 16 16 16 cks1, cks0 15 err cks1 cks0 pwcsr divr f. f. pot 2 2 2 2 3 pwc noise canceller en sw0 sw1 pwcr read error detection write enable reload data transfer overflow 16-bit up-count timer clock internal clock (machine clock/4) clock divider control circuit timer clear count enable divider clear flag set control bit output edge detec- tion divider on/off count start edge overflow interrupt request divide ratio selection 8-bit divider overflow f 2 mc-16lx bus count end interrupt request start edge selection count end edge end edge selection
mb90580c series ds07-13710-7e 49 7. 16-bit i/o timer the 16-bit i/o timer module consists of one 16-bit fr ee run timer, four input capture circuits, and two output comparators. this module allows two independent wavefo rms to be output on the basis of the 16-bit free run timer. input pulse width and external cl ock periods can, therefore, be measured. (1) 16-bit free-run timer (1 channel) the 16-bit free run timer consists of a 16-bit up-count er, a control register, and a prescaler. the value output from this timer/counter is used as the base time for the input capture and output compare modules. ? counter operation clock (selecta ble from among the following four) four internal clock cycles: /4, /16, /64, /256 : machine clock ? interrupts an interrupt can be generated when the 16-bit free-run ti mer causes a counter overflow or by compare/match operation with compare register 0. (the compar e/match operation requires the mode setting). ? counter value an interrupt can be generated when the 16-bit free-run timer causes a counter overflow or when a match with compare register 0 occurs (the compare/match functi on can be used by the appropriate mode setting). ? initialization the counter value can be initialized to ?0000 h ? at a reset, soft clear operation, or a match with compare register 0. (2) output compare module (2 channels) the output compare module consists of two 16-bit co mpare registers, compare output latches, and control registers. when the 16-bit free-run timer value matches the compare register value, this module generates an interrupt while inverting the output level. ? two compare registers can operate independently. output pin and interrupt flag for each compare register ? a pair of compare registers can be used to control the output pin. two compare registers can be used to invert the output pin polarity. ? the initial value for each output pin can be set. ? an interrupt can be generated by compare/match operation. (3) input capture module (4 channels) the input capture module consists of capture registers and control registers respecti vely associated with four independent external input pins. this mo dule can hold the 16-bit free run ti mer value in the capture register. in addition, it can detect an arbitrary edge of the signal input from each exter nal input pin to generate an interrupt. ? the external input signal edge to be detected can be selected. one or both of the rising and falling edges can be selected. ? four input capture channels can operate independently. ? an interrupt can be generated at a valid edge of the external input signal. the extended intelligent i/o service can be activate d by the interrupt by the input capture module.
mb90580c series 50 ds07-13710-7e (4) register configuration (continued) ? timer data register (upper) bit 15141312 11 10 9 8 address : 00006d h t15 t14 t13 t12 t11 t10 t09 t08 tcdth access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? timer data register (lower) bit 7654 3 210 address : 00006c h t07 t06 t05 t04 t03 t02 t01 t00 tcdtl access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? timer control status register bit 7654 3 210 address : 00006e h re- served ivf ivfe stop mode clr clk1 clk0 tccs access ( ? ) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? compare register (upper) bit 15 1413121110 9 8 occp0 occp1 address : ch0 00005b h c15 c14 c13 c12 c11 c10 c09 c08 : ch1 00005d h access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? compare register (lower) bit 7 6543210 occp0 occp1 address : ch0 00005a h c07 c06 c05 c04 c03 c02 c01 c00 : ch1 00005c h access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? compare control status register 1 bit 151413 12 1110 9 8 address : ch1 00005f h ??? cmod ote1 ote0 otd1 otd0 ocs1 access ( ? ) ( ? ) (? ) (r/w) (r/w) (r/w) (r/w) (r/w) initial value ( ? ) ( ? ) (? ) (0) (0) (0) (0) (0) ? compare control status register 0 bit 7 6 5 4 3 2 1 0 address : ch0 00005e h icp1 icp0 ice1 ice0 ?? cst1 cst0 ocs0 access (r/w) (r/w) (r/w) (r/w) ( ? ) ( ? ) (r/w) (r/w) initial value (0) (0) (0) (0) ( ? ) ( ? ) (0) (0)
mb90580c series ds07-13710-7e 51 (continued) ? input capture register (upper) bit 151413121110 98 address : ch0 000061 h : ch1 000063 h : ch2 000065 h : ch3 000067 h ipcp0 upper ipcp1 upper cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 ipcp2 upper ipcp3 upper access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? input capture register (lower) bit 76543210 address : ch0 000060 h ipcp0 lower : ch1 000062 h ipcp1 lower : ch2 000064 h cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 ipcp2 lower : ch3 000066 h ipcp3 lower access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? input capture control status register 01 bit 76543210 address : 000068 h icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 ics01 access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? input capture control status register 23 bit 76543210 address : 00006a h icp3 icp2 ice3 ice2 eg31 eg30 eg21 eg20 ics23 access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0)
mb90580c series 52 ds07-13710-7e (5) block diagram icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 t t q q cmod ote1 ote0 out0 out1 ivf ivfe stop mode clr clk1 clk0 in0, in2 in1, in3 edge detection compare control compare interrupt 0 compare interrupt 1 interrupt request comparator 0 16-bit up-counter output count value (t15 to t00) frequency divider clock f 2 mc-16lx bus compare register ch.0 compare control compare register ch.1 control block input capture data register ch.0, ch.2 input capture data register ch.1, ch.3 capture interrupt 1/3 capture interrupt 0/2 each control block edge detection
mb90580c series ds07-13710-7e 53 8. 16-bit reload timer the 16-bit reload timer has three channels, each of wh ich consists of a 16-bit down counter, a 16-bit reload register, an input pin (tin), an output pin (tot), and a control register. the input clock can be selected from among three internal clocks and one external clock. (1) register configuration ? timer control status register (upper) bit 151413121110 9 8 address : ch0 000049 h tmcsr0 upper : ch1 00004d h ???? csl1 csl0 mod2 mod1 tmcsr1 upper : ch2 000051 h tmcsr2 upper access ( ? ) ( ? ) (? ) (? ) (r/w) (r/w) (r/w) (r/w) initial value ( ? ) ( ? ) (? ) (? ) (0) (0) (0) (0) ? timer control status register (lower) bit 765432 1 0 address : ch0 000048 h tmcsr0 lower : ch1 00004c h mod0 oute outl reld inte uf cnte trg tmcsr1 lower : ch2 000050 h tmcsr2 lower access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? 16-bit timer register (upper) /16 bit reload register (upper) (read) bit 15 14 13 12 11 10 9 8 tmr0 upper address : ch0 00004b h tmr1 upper : ch1 00004f h tmr2 upper : ch2 000053 h (write) access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) tmrlr0 upper initial value (x) (x) (x) (x) (x) (x) (x) (x) tmrlr1 upper tmrlr2 upper ? 16-bit timer register (lower) /16 bit reload register (lower) (read) bit 765432 1 0 tmr0 lower address : ch0 00004a h tmr1 lower : ch1 00004e h tmr2 lower : ch2 000052 h (write) access (r/w) (r/w) (r/w) (r/w) (r /w) (r/w) (r/w) (r/w) tmrlr0 lower initial value (x) (x) (x) (x) (x) (x) (x) (x) tmrlr1 lower tmrlr2 lower
mb90580c series 54 ds07-13710-7e (2) block diagram out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 ctlin ? 2 ? 2 ? 2 135 3 exck gate irq reld oute outl inte uf cnte trg retrigger 16-bit reload register 16-bit down-counter uf reload clock selector machine clock prescaler clear clear ei 2 osclr port (tin) port (tot) serial baud rate (channel n) output enable f 2 mc-16lx bus note: reload timer channels and uart channels are connected as follows ?reload timer channel 0 : uart0, uart3 ?reload timer channel 1 : uart1, uart4 ?reload timer channel 2 : uart2
mb90580c series ds07-13710-7e 55 9. 8/16-bit ppg 8/16-bit ppg is an 8/16-bit reload timer module. the bl ock performs ppg output in which the pulse output is controlled by the operation of the timer. the hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. the ppg has the following functions. ? 8-bit ppg output in two channe ls independent operation mode: two independent ppg output channels are available. ? 16-bit ppg output operation mode : one 16-bit ppg output channel is available. ? 8 + 8-bit ppg output operation mode : variable-period 8-bit ppg output operation is available by using the output of channel 0 as the clock input to channel 1. ? ppg output operation : outputs pulse waveforms with variable period and duty ratio. can be used as a d/a converter in conjunction with an external circuit. (1) register configuration ? ppg0 operating mode control register bit 7654321 0 address : ch0 0000044 h pen0 ? poe0 pie0 puf0 ?? re- served ppgc0 access (r/w) ( ? ) (r/w) (r/w) (r/w) ( ? ) ( ? ) (r/w) initial value (0) (x) (0) (0) (0) (x) (x) (1) ? ppg1 operating mode control register bit 151413121110 9 8 address : ch1 0000045 h pen1 ? poe1 pie1 puf1 md1 md0 re- served ppgc1 access (r/w) ( ? ) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (x) (0) (0) (0) (0) (0) (1) ? ppg0 and 1 output control registers bit 7654321 0 address : ch0, 1 0000046 h pcs2 pcs1 pcs0 pcm2pcm1pcm0 re- served re- served ppgoe access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? reload register h bit 151413121110 9 8 address : ch0 000041 h prlh0 : ch1 000043 h prlh1 access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? reload register l bit 76543210 address : ch0 000040 h prll0 : ch1 000042 h prll1 access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x)
mb90580c series 56 ds07-13710-7e (2) block diagram ? block diagram (8 bit ppg ( ch.0 ) ) s r q prlbh0 ppgc0 prll0 prlh0 ppg0 pen0 irq pie0 puf0 machine clock divided by 16 machine clock divided by 8 machine clock divided by 4 machine clock divided by 2 machine clock count clock selection timebase counter output oscillation clock divided by 512 ppg0 output enable invert clear ppg0 output latch l/h select l/h selector pcnt (down-counter) reload (operation mode control) l-side data bus h-side data bus ch.1 borrow
mb90580c series ds07-13710-7e 57 ? block diagram (8/16 bit ppg ( ch.1 ) ) s r q prlbh1 ppgc1 prll1 prlh1 ppg1 pen1 irq pie puf machine clock divided by 16 machine clock divided by 8 machine clock divided by 4 machine clock divided by 2 machine clock ppg1 output enable l/h selector ch0 borrow a/d converter ppg1 output latch clear invert reload pcnt (down-counter) count clock selection timebase counter output oscillation clock divided by 512 (operation mode control) l-side data bus h-side data bus l/h select
mb90580c series 58 ds07-13710-7e 10. dtp/external interrupts the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16lx cpu. the dtp receives dma and interrupt processi ng requests from external peripherals and passes the requests to the f 2 mc-16lx cpu to activate the intelligent i/o serv ice or interrupt processing. two request levels (?h? and ?l?) are provided for the intelligent i/o service. for external interrupt requests, generation of interrupts on a rising or falling edge as well as on ?h? and ?l? le vels can be selected, giving a total of four types. (1) register configuration (2) block diagram ? interrupt/dtp enable register bit 76543210 address : 0000030 h en7 en6 en5 en4 en3 en2 en1 en0 enir access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? interrupt/dtp source register bit 151413121110 9 8 address : 0000031 h er7 er6 er5 er4 er3 er2 er1 er0 eirr access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? request level setting register (lower) bit 76543210 address : 0000032 h lb3 la3 lb2 la2 lb1 la1 lb0 la0 elvr lower access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? request level setting register (upper) bit 151413121110 9 8 address : 0000033 h lb7 la7 lb6 la6 lb5 la5 lb4 la4 elvr upper access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) 8 8 8 8 8 interrupt/dtp enable register interrupt/dtp source register request level setting register gate source f/f edge detect circuit request input f 2 mc-16lx bus
mb90580c series ds07-13710-7e 59 11. delayed interrupt generation module the delayed interrupt generation module is used to generat e the task switching interrupt. interrupt requests to the f 2 mc-16lx cpu can be generated and clea red by software using this module. (1) register configuration the dirr register controls generation and clearing of delayed interrupt requests. writing ?1? to the register generates a delayed interrupt request. wr iting ?0? to the register clears the delayed interrupt request. the register is set to the interrupt cleared state by a reset. either ?0? or ?1? can be written to the reserved bits. however, considering possible future extensions, it is recommended t hat the set bit and clear bit instructions are used for register access. (2) block diagram ? delayed interrupt generation/release register bit 151413121110 9 8 address : 00009f h ??????? r0 dirr access ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) initial value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (0) delayed interrupt generation/ release decode interrupt latch f 2 mc-16lx bus
mb90580c series 60 ds07-13710-7e 12. a/d converter the a/d converter converts analog input voltages to digi tal values. the a/d converter has the following features. ? conversion time: minimum of 34.7 s per channel (for a 12 mhz machine clock) ? uses rc-type successive approximation co nversion with a sample and hold circuit. ? 8/10-bit resolution ? eight program-selectable analog input channels single conversion mode: selectively convert one channel. scan conversion mode: continuously convert multiple channels. maximum of 8 program selectable channels. continuous conversion mode : re peatedly convert specified channels. stop conversion mode:convert one channel then halt until the next activation. (enables synchronization of the conversion start timing.) ? an a/d conversion completion interrupt request. an a/d conversion completion interrupt request to t he cpu can be generated on the completion of a/d conversion. this interrupt can activate ei 2 os to transfer the result of a/d conversion to memory and is suitable for continuous operation. ? activation by software, external trigger (falli ng edge), or timer (rising edge) can be selected. (1) register configuration ? control status register (upper) bit 151413121110 9 8 address : 000037 h busy int inte paus sts1 sts0 strt re- served adcs2 access (r/w) (r/w) (r/w) (r /w) (r/w) (r/w) (r/w) ( ?) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? control status register (lower) bit 76543210 address : 000036 h md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 adcs1 access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? data register (upper) bit 151413121110 9 8 address : 000039 h selb st1 st0 ct1 ct0 ? d9 d8 adcr2 access (w) (w) (w) (w) (w) ( ? ) (r) (r) initial value (0) (0) (0) (0) (1) ( ? ) (x) (x) ? data register (lower) bit 76543210 address : 000038 h d7 d6 d5 d4 d3 d2 d1 d0 adcr1 access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x)
mb90580c series ds07-13710-7e 61 (2) block diagram av cc avrh,avrl an0 an1 an2 an3 an4 an5 an6 an7 mpx adcr1, 2 adcs1, 2 adtg av ss sample and hold circuit comparator d/a converter data register successive approxi- mation register trigger activation control status register lower f 2 m c 1 6 l x b u s control status register upper timer activation operating clock ppg1 output decoder input circuit prescaler
mb90580c series 62 ds07-13710-7e 13. d/a converter d/a converter is an r-2r type d/a converter with 8-bit resolution. the device contains two d/a converters. the d/a control register controls the output of the two d/a converters independently. (1) register configuration ? d/a converter data register 1 bit151413121110 9 8 address : 00003b h da17 da16 da15 da14 da13 da12 da11 da10 dat1 access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? d/a converter data register 0 bit76543210 address : 00003a h da07 da06 da05 da04 da03 da02 da01 da00 dat0 access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? d/a control register 1 bit151413121110 9 8 address : 00003d h ??????? dae1 dacr1 access ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (? ) (? ) (r/w) initial value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (? ) (? ) (0) ? d/a control register 0 bit76543210 address : 00003c h ??????? dae0 dacr0 access ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (? ) (? ) (r/w) initial value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (? ) (? ) (0)
mb90580c series ds07-13710-7e 63 (2) block diagram da 17 da 16 da 15 da 14 da 13 da 12 da 11 da 10 da 07 da 06 da 05 da 04 da 03 da 02 da 01 da 00 dae1 2r 2r 2r 2r r r r dvr da17 da16 da15 da11 da10 dae0 2r 2r 2r 2r r r r dvr da07 da06 da05 da01 da00 2r 2r f 2 mc-16lx - bu s da output channel 1 da output channel 0 standby control standby control
mb90580c series 64 ds07-13710-7e 14. communication prescaler the register (clock division control register) of the co mmunication prescaler controls division of the machine clock frequency. it is designed to provide a fixed baud rate for a variety of machine clock frequencies depending on the user setting. the output from the communication prescaler is used by the uarts. (1) register configuration ? clock division control registers 0 to 4 bit 151413121110 9 8 address : 00002c h 00002e h 000034 h 000087 h 00008f h md ??? div3 div2 div1 div0 cdcr0 cdcr1 cdcr2 cdcr3 cdcr4 access (r/w) ( ? ) ( ? ) ( ? ) (r/w) (r/w) (r/w) (r/w) initial value (0) ( ? ) ( ? ) ( ? ) (1) (1) (1) (1)
mb90580c series ds07-13710-7e 65 15. uart the uart is a serial i/o port for asynchronous (start-stop) communication or clock-synchronous communication. the uart has the following features: ? full-duplex double buffering ? capable of asynchronous (start-s top) and clk-synchronous communications ? support for the multiprocessor mode ? dedicated baud rate generator integrated baud rate * : assuming internal machine clock fr equencies of 6, 8, 10, 12, and 16 mhz ? capable of setting an arbitrary baud rate using an external clock ? error detection functions (parity, framing, overrun) ? hrz sign transfer signal (1) register configuration operation baud rate asynchronous 31250/9615/4808/2404/1202 bps clk synchronous 2 m/1 m/5 00 k/250 k/125 k/62.5 kbps ? serial mode register 0 to 4 address : 0000020 h 0000024 h 0000028 h 0000082 h 0000088 h bit 76543210 smr0 smr1 smr2 smr3 smr4 md1 md0 cs2 cs1 cs0 re- served scke soe access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? serial control register 0 to 4 address : 0000021 h 0000025 h 0000029 h 0000083 h 0000089 h bit 151413121110 9 8 scr0 scr1 scr2 scr3 scr4 pen p sbl cl a/d rec rxe txe access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (1) (0) (0) ? serial input register 0 to 4/ serial output register 0 to 4 bit 76543210 (read) (write) address : 0000022 h 0000026 h 000002a h 0000084 h 000008a h d7 d6 d5 d4 d3 d2 d1 d0 sidr0 sidr1 sidr2 sidr3 sidr4 sodr0 sodr1 sodr2 sodr3 sodr4 access (r/w) (r/w) (r/w) (r/w ) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? serial status register 0 to 4 address : 0000023 h 0000027 h 000002b h 0000085 h 000008b h bit 151413121110 9 8 ssr0 ssr1 ssr2 ssr3 ssr4 pe ore fre rdrftdre ? rie tie access (r/w) (r/w) (r/w) (r/w) (r/w) ( ? ) (r/w) (r/w) initial value (0) (0) (0) (0) (1) ( ? ) (0) (0)
mb90580c series 66 ds07-13710-7e (2) block diagram sin0 sin4 sidr0 to sidr4 sodr0 to sodr4 md1 md0 cs2 cs1 cs0 scke soe sot0 to sot4 pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sck0 to sck4 control signals dedicated baud rate generator 16 bit reload timer channel 0 to 2 external clock clock select circuit receive condition decision circuit reception error generation signal for ei 2 os (to cpu) receive clock receive control circuit start bit detection circuit receive bit counter receive parity counter shift register for reception reception complete f 2 mc-16lx bus transmit clock receive interrupt signal (to cpu) transmit interrupt signal (to cpu) transmit start circuit transmit bit counter transmit parity counter shift register for transmission start transmission smr0 to smr4 register control signal scr0 to scr4 register ssr0 to ssr4 register transmit control circuit
mb90580c series ds07-13710-7e 67 16. iebus tm controller the iebus tm (inter-equipment bus) is a small-scale, two-wi re serial bus interface designed for data transfer between pieces of equipment. this interface is applicable, for example, as a bus interface for controlling vehicle-mounted devices. iebus tm has the following features: ?multitasking any of the units connected to the iebus tm can transmit data to another one. ? broadcast function (communication from one unit to multiple units) group broadcast : broadcast to a group of units all-unit broadcast : broadcast to all units ? three modes can be selected for different transmission speeds. ? data buffer for transmission 8-byte fifo buffer ? data buffer for reception 8-byte fifo buffer ? cpu internal operating frequency (12 mhz, 12.58 mhz) ? frequency tolerance in mode 0 or 1 : 1.5 % in mode 2 : 0.5 % (1) register configuration (continued) iebus tm internal frequency 6 mhz 6.29 mhz mode 0 about 3.9 kbps about 4.1 kbps mode 1 about 17 kbps about 18 kbps mode 2 about 26 kbps about 27 kbps ? local-office address setting register h bit 15 14 13 12 11 10 9 8 address : 000071 h reserved reserved reserved reserved ma11 ma10 ma09 ma08 mawh access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? local-office address setting register l bit7 6 5 43210 address : 000070 h ma07 ma06 ma05 ma04 ma03 ma02 ma01 ma00 mawl access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? slave address setting register h bit 15 14 13 12 11 10 9 8 address : 000073 h reserved reserved reserved reserved sa11 sa10 sa09 sa08 sawh access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x)
mb90580c series 68 ds07-13710-7e (continued) ? slave address setting register l bit7654321 0 address : 000072 h sa07 sa06 sa05 sa04 sa03 sa02 sa01 sa00 sawl access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? broadcast control bit setting register bit151413121110 9 8 address : 000075 h do3 do2 do1 do0 c3 c2 c1 c0 dcwr access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? broadcast control bit read register bit151413121110 9 8 address : 00007f h do3 do2 do1 do0 c3 c2 c1 c0 dcrr access (r) (r) (r) (r) (r) (r) (r) (r) initial value (0) (0) (0) (x) (x) (x) (x) (x) ? message length bit setting register bit7654321 0 address : 000074 h de7 de6 de5 de4 de3 de2 de1 de0 dewr access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (0) ? message length bit read register bit7654321 0 address : 00007e h de7 de6 de5 de4 de3 de2 de1 de0 derr access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? command register h bit151413121110 9 8 address : 000077 h md1 md0 pcom rie tie gotmgots reserved cmrh access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (0) (0) (0) (0) (0) (0) (0) (x) ? command register l bit7654321 0 address : 000076 h rxs txs tit1 tit0 cs1 cs0 rdbc wdbc cmrl access (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (1) (1) (0) (0) (0) (0) (0) (0) ? status register h bit151413121110 9 8 address : 000079 h com te pef ack rif tif tsl eod strh access (r) (r/w) (r) (r) (r/w) (r/w) (r) (r) initial value (0) (0) (x) (x) (0) (0) (0) (0)
mb90580c series ds07-13710-7e 69 (continued) ? status register l bit7654 3210 address : 000078 h wdbf rdbf wdbe rdbe st3 st2 st1 st0 strl access (r) (r) (r) (r) (r) (r) (r) (r) initial value (0) (0) (1) (1) (x) (x) (x) (x) ? lock read register h bit1514131211109 8 address : 00007b h reserved reserved reserved loc ld11 ld10 ld09 ld08 lrrh access (r) (r) (r) (r/w) (r) (r) (r) (r) initial value (1) (1) (1) (0) (x) (x) (x) (x) ? lock read register l bit7654 3210 address : 00007a h ld07 ld06 ld05 ld04 ld03 ld02 ld01 ld00 lrrl access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? master address read register h bit1514131211109 8 address : 00007d h reserved reserved reserved reserved ma11 ma10 ma09 ma08 marh access (r) (r) (r) (r) (r) (r) (r) (r) initial value (1) (1) (1) (1) (x) (x) (x) (x) ? master address read register l bit7654 3210 address : 00007c h ma07 ma06 ma05 ma04 ma03 ma02 ma01 ma00 marl access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? read data buffer bit1514131211109 8 address : 000081 h rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 rdb access (r) (r) (r) (r) (r) (r) (r) (r) initial value (x) (x) (x) (x) (x) (x) (x) (x) ? write data buffer bit7654 3210 address : 000080 h wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 wdb access (w) (w) (w) (w) (w) (w) (w) (w) initial value (x) (x) (x) (x) (x) (x) (x) (x)
mb90580c series 70 ds07-13710-7e (2) block diagram the control circuit in the iebus tm controller executes the following control functions: ? controls the number of bytes in data to be transmitted and received. ? controls the maximum number of bytes transmitted. ? detects the results of arbitration. ? evaluates the return of acknowledgment of each field. ? generates interrupt signals. 2 tx rx 6 mhz/6.29 mhz local-office address setting register slave address setting register broadcast control bit setting register message length bit setting register 8-byte fifo, write data buffer master address read register broadcast control bit read register message length bit read register lock read register 8-byte fifo, read data buffer command register status register f 2 mc-16lx internal bus control circuit iebus tm protocol controller prescaler iebus tm controller interrupt request signal (transmission/reception) internal clock 12 mhz/12.58 mhz
mb90580c series ds07-13710-7e 71 17. clock monitor function the clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from the ckot pin. (1) register configuration (2) block diagram ? clock output enable register bit 76543210 address : 00003e h ???? cken frq2 frq1 frq0 clkr access ( ? ) ( ? ) ( ? ) ( ? ) (r/w) (r/w) (r/w) (r/w) initial value ( ? ) ( ? ) ( ? ) ( ? ) (0) (0) (0) (0) cken frq2 frq1 frq0 p65/ckot f 2 mc-16lx bus divider circuit machine clock
mb90580c series 72 ds07-13710-7e 18. address match detection function when an address matches the value set in the address detection register, the instruction code to be loaded into the cpu is forced to be replaced with the int9 instruct ion code (01h). when execut ing a set instruction, the cpu executes the int9 instruction. the address match detection function is implemented by processing using the int9 interrupt routine. the device contains two address detection registers, each provided with a compare enable bit. when the value set in the address detection register matches an address and the interrupt enab le bit is ?1?, the instruction code to be loaded into the cpu is forced to be replaced with the int9 instruction code. (1) register configuration ? program address detection register 0 to 2 (padr0) bit padr0 (lower) address : 001ff0 h access initial value bit padr0 (middle) address : 001ff1 h access initial value bit padr0 (upper) address : 001ff2 h access initial value ? program address detection register 3 to 5 (padr1) bit padr1 (lower) address : 001ff3 h access initial value bit padr1 (middle) address : 001ff4 h access initial value bit padr1 (upper) address : 001ff5 h access initial value ? program address detection cont rol/status register (pacsr) bit 76543210 address : 00009e h re- served re- served re- served re- served ad1e re- served ad0e re- served access ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( ? ) (r/w) ( ? ) initial value (0) (0) (0) (0) (0) (0) (0) (0) 76543210 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 17 16 15 14 13 12 11 10 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 17 16 15 14 13 12 11 10 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 17 16 15 14 13 12 11 10 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x)
mb90580c series ds07-13710-7e 73 (2) block diagram address latch address detection register enable bit int9 instruction f 2 mc-16lx cpu core f 2 mc-16lx bus compare
mb90580c series 74 ds07-13710-7e 19. rom mirroring function selection module the rom mirroring function selection module can select what the ff bank allocated the rom sees through the 00 bank according to register settings. (1) register configuration (2) block diagram ? rom mirroring function selection register bit151413121110 9 8 address : 00006f h ??????? mi romm access ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (? ) (? ) (w) rom address area data ff bank 00 bank address f 2 mc-16lx bus rom mirroring function selection register
mb90580c series ds07-13710-7e 75 20. one-megabit flash memory the 1mbit flash memory is allocated in the fe h to ff h banks on the cpu memory map. like masked rom, flash memory is read-accessible and program-accessible to the cpu using the flash memory interface circuit. the flash memory can be programmed/erased by the inst ruction from the cpu via the flash memory interface circuit. the flash memory can therefore be reprogrammed (updated) while still on the circuit board under inte- grated cpu control, allowing program code and data to be improved efficiently. note that sector operations such as ?enable sector protect? cannot be used. features of 1mbit flash memory ? 128k words x 8 bits or 64k words x 16 bits (1 6k + 8k x 2 + 32k + 64k) sector configuration ? automatic program algorithm (embedded algorithm: same as the mbm29f400ta) ? erasure suspend/resume function integrated ? detection of programming/erasure comple tion using the data polling or toggle bit ? detection of programming/erasure completion using cpu interrupts ? compatible with jedec standard commands ? capable of erasing data sector by se ctor (arbitrary combination of sectors) ? minimum number of times of programming/erasure: 10,000 (1) register configuration ? flash memory cont rol status register bit76543210 address : 0000ae h inte rdy- int we rdy reserved lpm1 reserved lpm0 fmcs access (r/w) (r/w) (r/w) (r) (w) (r/w) (w) (r/w) initial value (0) (0) (0) (x) (0) (0) (0) (0)
mb90580c series 76 ds07-13710-7e (2) sector configuration of 1mbit flash memory the 1mbit flash memory has the sector configuration illu strated below. the addresses in the illustration are the upper and lower addresses of each sector. when accessed from the cpu, sa0 and sa1 to sa4 are allo cated in the fe and ff bank registers, respectively. * : programmer addresses correspond to cpu addresses when data is programmed in flash memory by a parallel programmer. programmer addresses are used to program/erase data using a general-purpose programmer. flash memory cpu address programmer address * ffffff h 7ffff h sa4 (16 kbytes) ffc000 h 7c000 h ffbfff h 7bfff h sa3 (8 kbytes) ffa000 h 7a000 h ff9fff h 79fff h sa2 (8 kbytes) ff8000 h 78000 h ff7fff h 77fff h sa1 (32 kbytes) ff0000 h 70000 h feffff h 6ffff h sa0 (64 kbytes) fe0000 h 60000 h
mb90580c series ds07-13710-7e 77 21. low-power consumption control circuit the operation modes of the mb90580c se ries are the pll clock, pll sleep, watch, main clock, main sleep, stop, and hardware standby modes. the operation modes e xcluding the pll clock mode are classified as low- power consumption modes. the low power consumption circuit has the following functions. ? main clock mode/main sleep mode in either mode, the microcontroller operates only with the main clock (osc oscillation clock), using the main clock as the operating clock while suspendi ng the pll clock (vco oscillation clock). ? pll sleep mode/main sleep mode these modes stop only the operation clock of the cpu, leaving the other clocks active. ? watch mode the watch mode allows only the time-base timer to operate. ? stop mode/hardware standby mode these modes stop oscillation while retaining data at the lowest power consumption. the cpu intermittent operation function causes the clock supplied to the cpu to operate intermittently when the cpu accesses a register, internal memory, internal resource, or exter nal bus. this function saves power consumption by de- creasing the execution speed of the cpu while providing high-speed clock signals to the internal resources. the pll clock multiplication factor can be selected from among 1, 2, 3, and 4 us ing the cs1 and cs0 bits in the clock selection register. the ws1 and ws0 bits can be used to set the oscillation settling time for the main clock, which is taken to wake up from the stop or hardware standby mode. (1) register configuration ? low-power consumption mode control register bit 76543210 address : 0000a0 h stp slp spl rst tmd cg1 cg0 ? lpmcr access (w) (w) (r/w) (w) ( ? ) (r/w) (r/w) ( ?) initial value (0) (0) (0) (1) (1) (0) (0) ( ?) ? clock selection register bit 151413121110 9 8 address : 0000a1 h scm mcm ws1 ws0 scs mcs cs1 cs0 ckscr access (r) (r) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value (1) (1) (1) (1) (1) (1) (0) (0)
mb90580c series 78 ds07-13710-7e (2) block diagram mcm mcs cs1 cs0 cg1 cg0 slp stp tmd 1234 rst scm sleep stop mstp ws1 ws0 spl rst 2 10 2 13 2 15 2 18 2 19 2 16 2 14 2 12 lpmcr lpmcr ckscr ckscr scm scs ckscr ckscr lpmcr lpmcr wdgrst 1/2 s sub clock switching controller cpu clock selector oscillation stability waiting time selector hst start standby control circuit cpu intermittent operation cycle selector pll multiplication circuit pin hi-impedance control circuit internal reset generation signal circuit cpu clock generation cpu clock 0/9/17/33 intermittent cycle selection peripheral clock generation sub clock (osc oscillation) interrupt request or rst sub osc stop main osc stop peripheral clock to watchdog timer internal rst rst pin pin hi-z clock input timebase timer f 2 mc-16lx bus cancel hst pin main clock (osc oscillation)
mb90580c series ds07-13710-7e 79 electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : care must be taken that av cc , avrh, avrl, dv cc do not exceed v cc . also, care must be taken that avrh, avrl do not exceed av cc , and avrl does not exceed avrh. *2 : v i and v o shall never exceed v cc + 0.3 v. *3 : the maximum output current is a peak value for a corresponding pin. *4 : ? applicable to pins: p00 to p07, p10 to p17, p20 to p2 7, p30 to p37, p40 to p47, p60 to p65, p71, p72, p80 to p87, p90 to p97, pa0 to pa2, rx ? use within recommended operating conditions. ? use at dc voltage (current) ? the + b signal should always be applied with a limiting resistance placed between the +b signal and the microcontroller. (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc av cc * 1 avrh, avrl v ss ? 0.3 v ss + 6.0 v av cc avrh/l, avrh avrl dv cc v ss ? 0.3 v ss + 6.0 v v cc dv cc input voltage v i v ss ? 0.3 v ss + 6.0 v *2 output voltage v o v ss ? 0.3 v ss + 6.0 v *2 maximum clamp current i clamp ? 2.0 + 2.0 ma *4 total maximum clamp current | i clamp | ? 20 ma *4 ?l? level maximum output current i ol ? 15 ma *3 ?l? level average output current i olav ? 4ma average output current = operating current operating efficiency ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma average output current = operating current operating efficiency ?h? level maximum output current i oh ?? 15 ma *3 ?h? level average output current i ohav ?? 4ma average output current = operating current operating efficiency ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current i ohav ?? 50 ma average output current = operating current operating efficiency power consumption p d ? 300 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb90580c series 80 ds07-13710-7e (continued) ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pins does not exceed rated val ues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided fr om the pins and the resulting supply voltage may not be suffici ent to operate th e power-on reset. ? care must be taken not to leave the +b input pin open. ? note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. ? input/output equivalent circuits p-ch n-ch v cc r + b input (0 v to 16 v) limiting resistance protective diode
mb90580c series ds07-13710-7e 81 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 5.5 v normal operation (mb90583c/ca, mb90587c/ca, mb90v580b) 4.5 5.5 v normal operation (mb90f583c/ca, mb90f584c/ca) v cc 3.0 5.5 v retains status at the time of operation stop ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihm v cc ? 0.3 v cc + 0.3 v md pin input ?l? level input voltage v il v ss ? 0.3 0.3 v cc v cmos input pin v ils v ss ? 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss ? 0.3 v ss + 0.3 v md pin input smoothing capacitor c s 0.1 1.0 f use a ceramic capacitor or a capacitor with equiv- alent frequency characteristics. the smoothing ca- pacitor to be connected to the v cc pin must have a capacitance value higher than c s . operating temperature t a ? 40 + 85 c ? c pin connection circuit c c s
mb90580c series 82 ds07-13710-7e 3. dc characteristics (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level output voltage v oh all output pins v cc = 4.5 v, i oh = ?2.0 ma v cc ? 0.5 ?? v ?l? level output voltage v ol all output pins v cc = 4.5 v, i ol = 2.0 ma ?? 0.4 v input leakage current i il all input pins v cc = 5.5 v, v ss < v i < v cc ?5 ? 5 a power supply current* i cc v cc v cc = 5.0 v, internal operation at 16 mhz, normal operation ? 27 33 ma mb90583c/ca, mb90587c/ca ? 40 50 ma mb90f583c/ca, mb90f584c/ca v cc = 5.0 v, internal operation at 12.58 mhz, normal operation ? 22 26 ma mb90583c/ca ? 35 45 ma mb90f583c/ca, mb90f584c/ca v cc = 5.0 v, internal operation at 16 mhz, when data written in flash mode pro- gramming of erasing ? 45 60 ma mb90f583c/ca, mb90f584c/ca v cc = 5.0 v, internal operation at 12.58 mhz, when data written in flash mode pro- gramming of erasing ? 40 50 ma i ccs v cc = 5.0 v, internal operation at 16 mhz, in sleep mode ? 7 12 ma mb90587c/ca ? 15 20 ma mb90583c/ca, mb90f583c/ca, mb90f584c/ca v cc = 5.0 v internal operation at 12.58 mhz, in sleep mode ? 6 10 ma mb90587c/ca ? 12 18 ma mb90583c/ca, mb90f583c/ca, mb90f584c/ca i ccl v cc = 5.0 v, internal operation at 8 khz, subsystem operation, t a = 25 c ? 0.1 1.0 ma mb90583c, mb90587c ? 4 7 ma mb90f583c/f584c
mb90580c series ds07-13710-7e 83 (continued) (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) *: the current value is preliminary value and may be subj ect to change for enhanced characteristics without previous notice. the power supply current is measured with an external clock. parameter symbol pin name condition value unit remarks min typ max power supply current* i ccls v cc v cc = 5.0 v, internal operation at 8 khz, in subsleep mode, t a = 25 c ? 30 50 a mb90583c, mb90587c, mb90f583c/f584c i cct v cc = 5.0 v, internal operation at 8 khz, in clock mode, t a = 25 c ? 15 30 a mb90583c, mb90587c, mb90f583c/f584c i cch in stop mode, t a = 25 c ? 520 a mb90583c/ca mb90587c/ca, mb90f583c/ca, mb90f584c/ca input capacitance c in except av cc , av ss , c, v cc and v ss ?? 10 80 pf open-drain output leakage current i leak p40 to p47 ?? 0.1 5 a open-drain output setting pull-up resistance r up p00 to p07 p10 to p17 p60 to p65 rst ? 25 50 100 k pull-down resistance r down md2 ? 25 50 100 k
mb90580c series 84 ds07-13710-7e 4. ac characteristics (1) clock timings (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condi- tion value unit remarks min typ max clock frequency f c x0, x1 ? 3 ? 16 mhz not multiplied, when using oscillation circuit. 8 ? 16 pll multiplied 1, when using oscillation circuit. 4 ? 8 pll multiplied 2, when using oscillation circuit. 3 ? 5.3 pll multiplied 3, when using oscillation circuit. 3 ? 4 pll multiplied 4, when using oscillation circuit. f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 62.5 ? 333 ns t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh p wl x0 10 ?? ns recommended duty ratio of 30% to 70% p wlh p wll x0a ? 15.2 ? s input clock rise/fall time t cr t cf x0 ?? 5ns external clock operation internal operating clock frequency f cp ? 1.0 ? 16 mhz main clock operation f lcp ?? 8.192 ? khz sub clock operation internal operating clock cycle time t cp ? 62.5 ? 666 ns main clock operation t lcp ?? 122.1 ? s sub clock operation x0 t hcyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl ? x0, x1 clock timing x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll ? x0a, x1a clock timing
mb90580c series ds07-13710-7e 85 the ac ratings are measured for the following measurement reference voltages ? pll operation guarantee range 5.5 4.5 3.3 3.0 16 12 8 9 4 3 4 8 16 1.5 38 12 16 power supply voltage v cc (v) operation guarantee range of pll operation guarantee range of mb90583c/ca, mb90587c/ca, mb90v580b internal clock f cp (mhz) relationship between intern al operating clock frequency and power supply voltage operation guarantee range of mb90f583c/ca, mb90f584c/ca relationship between oscillating frequency and internal operating clock frequency oscillation clock f c (mhz) internal clock f cp (mhz) not multiplied multiplied- by-4 multiplied- by-3 multiplied- by-2 multiplied- by-1 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hystheresis input pin pins other than hystheresis input/md input ? output signal waveform output pin
mb90580c series 86 ds07-13710-7e (2) clock output timings (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) (3) reset, hardware standby input timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condition value unit remarks min max clock cycle time t cyc clk v cc = 5 v 10 % 62.5 ? ns clk clk t chcl 20 ? ns parameter symbol pin name condition value unit remarks min max reset input time t rstl rst ? 4 t cp ? ns hardware standby input time t hstl hst 4 t cp ? ns clk t cyc 2.4 v 2.4 v 0.8 v t chcl rst hst 0.2 v cc t rstl , t hstl 0.2 v cc
mb90580c series ds07-13710-7e 87 (4) power-on reset (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) * : vcc must be kept lower than 0.2 v before power-on. note: the above values are used for causing a power-on reset. if hst = ?l?, be sure to turn the power supply on using the above values to cause a power-on reset whether or not the power-on reset is required. some registers in the device are initialized only upon a po wer-on reset. to initialize these registers, turn the power supply using the above values. parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply cut-off time t off v cc 4 ? ms wait time until power-on v cc v cc v ss 3.0 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recom- mended to raise the voltage smoothly to su ppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the volt- age drop is 1 v or fewer per second, however, you can use the pll clock. it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. ram data hold
mb90580c series 88 ds07-13710-7e (5) bus timing (read) (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condition value unit remarks min max ale pulse width t lhll ale ? t cp /2 ? 20 ? ns effective address ale time t avll ale, a23 to a16, ad15 to ad00 t cp /2 ? 20 ? ns ale address effective time t llax ale, ad15 to ad00 t cp /2 ? 15 ? ns effective address rd time t avrl a23 to a16, ad15 to ad00, rd t cp ? 15 ? ns effective address valid data input t avdv a23 to a16, ad15 to ad00 ? 5 t cp /2 ? 60 ns rd pulse width t rlrh rd 3 t cp /2 ? 20 ? ns rd valid data input t rldv rd , ad15 to ad00 ? 3 t cp /2 ? 60 ns rd data hold time t rhdx rd , ad15 to ad00 0 ? ns rd ale time t rhlh rd , ale t cp /2 ? 15 ? ns rd address effective time t rhax ale, a23 to a16 t cp /2 ? 10 ? ns effective address clk time t avch a23 to a16, ad15 to ad00, clk t cp /2 ? 20 ? ns rd clk time t rlch rd , clk t cp /2 ? 20 ? ns ale rd time t llrl ale, rd t cp /2 ? 15 ? ns
mb90580c series ds07-13710-7e 89 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc clk ale rd a23 to a16 ad15 to ad00 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv ? bus timing (read) address read data
mb90580c series 90 ds07-13710-7e (6) bus timing (write) (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condition value unit remarks min max effective address wr h , wrl time t avwl a23 to a16, ad15 to ad00, wrh, wrl ? t cp ? 15 ? ns wrh , wrl pulse width t wlwh wrh , wrl 3 t cp /2 ? 20 ? ns effective data output wrh , wrl time t dvwh ad15 to ad00, wrh , wrl 3 t cp /2 ? 20 ? ns wrh , wrl data hold time t whdx wrh , wrl , ad15 to ad00 20 ? ns wrh , wrl address effective time t whax wrh , wrl , a23 to a16 t cp /2 ? 10 ? ns wrh , wrl ale time t whlh wrh , wrl , ale t cp /2 ? 15 ? ns wrh , wrl clk time t wlch wrh , wrl , clk t cp /2 ? 20 ? ns 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale a23 to a16 ad15 to ad00 t whlh t avwl t wlwh t whax t whdx t wlch t dvwh wrh, wrl address write data ? bus timing (write)
mb90580c series ds07-13710-7e 91 (7) ready input timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) note: use the automatic ready function when the setup time for the rising edge of the rdy signal is not sufficient. parameter symbol pin name condition value unit remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh ? 0 ? ns t ryhh 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc clk ale rd/ t ryhs t ryhs wrh/ wrl rdy (wait not inserted) rdy (wait inserted)
mb90580c series 92 ds07-13710-7e (8) hold timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) note: more than 1 machine cycle is needed before hak changes after hrq pin is fetched. parameter symbol pin name condition value unit remarks min max pins in floating status hak time t xhal hak ? 30 t cp ns hak pin valid time t hahv hak t cp 2 t cp ns hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v pins high impedance
mb90580c series ds07-13710-7e 93 (9) uart0 to uart4 (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) notes : ? these are ac ratings in the clk synchronous mode. ? cl is the load capacitance value connected to pins while testing. ? t cp is machine cycle time (unit: ns). parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc sck0 to sck4 c l = 80 pf + 1 ttl for an output pin of internal shift clock mode 8 t cp ? ns sck sot delay time t slov sck0 to sck4, sot0 to sot4 ? 80 80 ns valid sin sck t ivsh sck0 to sck4, sin0 to sin4 100 ? ns sck valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck4 c l = 80 pf + 1 ttl for an output pin of external shift clock mode 4 t cp ? ns serial clock ?l? pulse width t slsh sck0 to sck4 4 t cp ? ns sck sot delay time t slov sck0 to sck4, sot0 to sot4 ? 150 ns valid sin sck t ivsh sck0 to sck4, sin0 to sin4 60 ? ns sck valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ? ns
mb90580c series 94 ds07-13710-7e sck sot sin sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? internal shift clock mode ? external shift clock mode
mb90580c series ds07-13710-7e 95 (10)timer input timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) (11) timer output timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condition value unit remarks min max input pulse width t tiwh t tiwl in0 to in3, tin0 to tin2 ? 4 t cp ? ns parameter symbol pin name condition value unit remarks min max clk t out transition time t to out0, out1, ppg0, ppg1, tot0 to tot2 ? 30 ? ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 2.4 v clk t out 0.8 v 2.4 v t to
mb90580c series 96 ds07-13710-7e (12) trigger input timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl irq0 to irq7, adtg ? 5 t cp ? ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
mb90580c series ds07-13710-7e 97 (13) iebus tm timing (v cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin name condition value unit remarks min max tx rx delay time (rise) t dly1 tx, rx ? 0 1000 ns tx rx delay time (fall) t dly2 tx, rx 0 1000 ns 0.7 v cc tx rx 0.3 v cc 0.7 v cc 0.3 v cc t dly1 t dly2 mb90580c series tx rx tx rx bus+ bus? iebus tm driver/ receiver
mb90580c series 98 ds07-13710-7e 5. a/d converter electrical characteristics (3.0 v avrh ? avrl, v cc = av cc = 5.0 v10 % , v ss = av ss = 0.0 v, t a = ?40 c to +85 c) * : the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avrh = 5.0 v) note: ? the error increases proportionally as |avrh - avrl| decreases. ? the output impedance of the external circuits connected to the analog inputs should be in the following range. ?the output impedance of the ex ternal circuit : 15.5 k (max) (sampling time = 4.0 s) ? if the output impedance of the external circuit is too high, the sampling time might be insufficient. parameter symbol pin name value unit remarks min typ max resolution ?? ? 10 ? bit total error ?? ? ? 5.0 lsb non-linear error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 avrl ? 3.5 lsb avrl + 0.5 lsb avrl + 4.5 lsb v 1 lsb = (avrh - avrl)/ 1024 full-scale transition voltage v fst an0 to an7 avrh ? 6.5 lsb avrh ? 1.5 lsb avrh + 1.5 lsb v compare time ?? 352 t cp ?? ns at machine clock = 16 mh z sampling period ?? 64 t cp ?? ns at machine clock = 16 mh z analog port input current i ain an0 to an7 ?? 10 a analog input voltage v ain an0 to an7 avrl ? avrh v reference voltage ? avrh avrl + 3.0 ? av cc v ? avrl 0 ? avrh ? 3.0 v power supply current i a av cc ? 5 ? ma i ah av cc ?? 5 a* reference voltage supply current i r avrh ? 400 ? a i rh avrh ?? 5 a* offset between channels ? an0 to an7 ?? 4lsb c 0 c 1 analog input comparator
mb90580c series ds07-13710-7e 99 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter linearity error: the deviation of the straight line connecting the zero transition point (?00 0000 0000? ? ?00 0000 0001?) with the full-scale transition point (?11 1111 1110? ? ?11 1111 1111?) from actual con- version characteristics differential linearity error: the deviation of input volt age needed to change the output code by 1 lsb from the theoretical value total error: the total error is define d as a difference between the actual va lue and the theoretical value, which includes zero-transition error/full-scal e transition error and linearity error. (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 0.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} total error actual conversion value analog input total error for digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (theoretical value) avrh ? avrl 1024 [v] v ot (theoretical value) = avrl + 0.5 lsb [v] v fst (theoretical value) = avrh ? 1.5 lsb [v] v nt : voltage at a transition of digi tal output from (n - 1) to n actual conversion value theoretical characteristics (measured value) digital output
mb90580c series 100 ds07-13710-7e (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v nt v nt v (n + 1)t v ot v fst {1 lsb (n ? 1) + v ot } linearity error theoretical characteristics (measured value) digital output differential linearity error (measured value) (measured value) linearity error of digital output n v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 lsb[lsb] = v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at transition of digital output from ?000 h ? to ?001 h ? v fst : voltage at transition of digital output from ?3fe h ? to ?3ff h ? actual conversion value actual conversion value actual conversion value actual conversion value theoretical characteristics (measured value) (measured value) digital output analog input analog input
mb90580c series ds07-13710-7e 101 7. notes on using a/d converter select the output impedance value for the external circui t of analog input according to the following conditions. output impedance values of the external circuit of 15.5 k or lower are recommended. when capacitors are connected to external pins, the capa citance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 mhz) ? error the smaller the | avrh - avrl |, the gr eater the error would become relatively. 8. d/a converter electrical characteristics (v cc = av cc = 5.0 v 10 % , v ss = av ss = dv ss = 0.0 v, t a = ?40 c to +85 c) *1 : load capacitance: 20 pf *2 : in sleep mode parameter symbol pin name value unit remarks min typ max resolution ?? ? 8 ? bit differential linearity error ?? ? ? 0.9 lsb absolute accuracy ?? ? ? 1.2 % linearity error ?? ? ? 1.5 lsb conversion time ?? ? 10 20 s*1 analog reference voltage ? dvrh v ss + 3.0 ? av cc v reference voltage supply current i dvr dvrh ? 120 300 a i dvrs ?? 10 a*2 analog output impedance ?? ? 20 ? k ? equipment of analog input circuit model c 0 c 1 analog input comparator note: listed values must be considered as standards. mb90587c/ca, mb90v580b r ? 1.5 k , c ? 30 pf mb90f583c/ca, mb90f584c/ca r ? 3.0 k , c ? 65 pf mb90583c/ca r ? 2.2 k , c ? 45 pf
mb90580c series 102 ds07-13710-7e 9. flash memory program/erase characteristics parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 3.0 v ? 115s excludes 00h programming prior erasure chip erase time ? 7 ? s excludes 00h programming prior erasure word (16 bit width) programming time ? 16 3,600 s excludes system-level overhead erase/program cycle ? 10,000 ? cycle
mb90580c series ds07-13710-7e 103 example characteristics ? power suppy current of mb90f583c/ca (continued) v cc (v) i ccs (ma) 20 15 10 5 0 23456 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz v cc (v) i cc (ma) 45 40 35 30 25 20 15 10 5 0 23456 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz v cc (v) i ccl (a) 500 450 400 350 300 250 200 150 100 50 0 23 456 f = 8 khz v cc (v) i ccls (a) 50 45 40 35 30 25 20 15 10 5 0 23456 f = 8 khz i cc vs. v cc t a = 25 c, external clock input i ccl vs. v cc t a = 25 c, external clock input (mb90f583c only) i ccs vs. v cc t a = 25 c, external clock input i ccls vs. v cc t a = 25 c, external clock input (mb90f583c only)
mb90580c series 104 ds07-13710-7e (continued) v cc - v oh (mv) i oh (ma) 1000 900 800 700 600 500 400 300 200 100 0 0 1 357911 2 4 6 8 10 12 v ol (v) i ol (ma) 1000 900 800 700 600 500 400 300 200 100 0 0 146 810 12 2 35 7 9 11 v oh vs. i oh t a = 25 c, v cc = 4.5 v v ol vs. i ol t a = 25 c, v cc = 4.5 v v cc (v) i cct (a) 30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 23456 f = 8 khz i cct vs. v cc t a = 25 c, external clock input (mb90f583c only)
mb90580c series ds07-13710-7e 105 power supply current of mb90583c/ca (continued) v cc (v) i cc (ma) 30 25 20 15 10 5 0 23456 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz v cc (v) i ccs (ma) 20 15 10 5 0 23456 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz v cc (v) i ccl (a) 70 60 50 40 30 20 10 0 23456 f = 8 khz v cc (v) i ccls (a) 50 45 40 35 30 25 20 15 10 5 0 23456 f = 8 khz i cc vs. v cc t a = 25 c, external clock input i ccl vs. v cc t a = 25 c, external clock input (mb90583c only) i ccs vs. v cc t a = 25 c, external clock input i ccls vs. v cc t a = 25 c, external clock input (mb90583c only)
mb90580c series 106 ds07-13710-7e (continued) v cc - v oh (mv) i oh (ma) 1000 900 800 700 600 500 400 300 200 100 0 01 2 3 4 56 7 8 91011 12 v ol (v) i ol (ma) 1000 900 800 700 600 500 400 300 200 100 0 0 1 23 456 789 10 11 12 v oh vs. i oh t a = 25 c, v cc = 4.5 v v ol vs. i ol t a = 25 c, v cc = 4.5 v v cc (v) i cct (a) 30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 23456 f = 8 khz i cct vs. v cc t a = 25 c, external clock input (mb90583c only)
mb90580c series ds07-13710-7e 107 ordering information part number package remarks MB90F583CPMC mb90f583capmc mb90583cpmc mb90583capmc mb90f584cpmc mb90f584capmc mb90587cpmc mb90587capmc 100-pin plastic lqfp (fpt-100p-m20) mb90f583cpf mb90f583capf mb90583cpf mb90583capf mb90f584cpf mb90f584capf mb90587cpf mb90587capf 100-pin plastic qfp (fpt-100p-m06)
mb90580c series 108 ds07-13710-7e package dimensions please confirm the latest pack age dimension by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 100-pin plastic lqfp lea d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 mm 14.0 mm lea d s h a pe gu llwing s e a ling method plastic mold mounting height 1.70 mm ma x weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin plastic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujitsu limited f100031s-c-2-1 14.00 0.10(.551 .004)sq 16.000.20(.630 .008)sq 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.008 .002) m 0.08(.003) 0.145 0.055 (.0057 .0022) 0.08(.003) "a" index .059 ? .004 +.008 ? 0.10 +0.20 1.50 (mounting height) 0 ? ~8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) details of "a" part (stand off) * dimens ion s in mm (inche s ). note: the v a l u e s in pa renthes e s a re reference va l u e s ?2005-2008 fujits u microelectronics limited f10003 1 s -c-2-2 note 1) * : these dimensions do not include resin protrusion. note 2) pin s width a nd pins thickness inclu de pla ting thickness. note 3 )pin s width do not inclu de tie bar cutting rema inder.
mb90580c series ds07-13710-7e 109 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 100-pin plas tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm lea d s h a pe gu llwing s e a ling method plastic mold mounting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin plas tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 ?0.20 +.014 ?.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * * dimens ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2002-2008 fujits u microelectronics limited f100008s -c-5-6 note 1) * : these dimensions do not include resin protrusion. note 2) pin s width a nd pins thickness inclu de pla ting thickness. note 3 ) pin s width do not inclu de tie bar cu tting rema inder.
mb90580c series 110 ds07-13710-7e main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 79 electrical characteristics 1. absolute maximum ratings corrected the *4. p71 to p74 p71, p72 84 electrical characteristics 4. ac characteristics (1) clock timings changed the row of ?clock frequency?. deleted the row of ?frequency fluctuation rate locked*?. corrected the minimum value of ?internal operating clock frequency?. 1.5 1.0 deleted ?*: the frequency fluctuation rate is the maximum deviation rate of the pres et center frequency when the multiplied pll signal is locked.? and the figure. 85 electrical characteristics 4. ac characteristics (1) clock timings ? pll operation guarantee range corrected the figure of ?relationship between internal operating clock frequency and power supply voltage?. 87 electrical characteristics 4. ac characteristics (4) power-on reset corrected the remarks column of ?power supply cut-off time?. due to repeated operations wait time until power-on
mb90580c series ds07-13710-7e 111 memo
mb90580c series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg ., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fa x : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porating the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectronics warrant non-i nfringement of any third-party's intellectual property right o r other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

▲Up To Search▲

Price & Availability of MB90F583CPMC

	To Download MB90F583CPMC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .